From: wdenk Date: Sun, 21 Oct 2001 10:54:46 +0000 (+0000) Subject: Several patches by Erik Theisen, 14 Oct 2001: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=760d1701c8cbd85bae5bbe3158ea6e70e208650e;p=users%2Frw%2Fppcboot.git Several patches by Erik Theisen, 14 Oct 2001: --------------------------------------------- - Fix udelay() for longer delays - Fix wait_ticks() - don't treat timebase registers as signed - Fix command name conflicts due to abbreviated length - Add support for Apple's OS X host environment - Add support for IBM 4xx DCR registers (commands "getdcr" and "setdcr" to read and read/modify/write the 4xx DCR) - Sort command table alphabetically and in descending string length order to prevent conflicts; added doc/README.commands - add "reset" option to help info for "date" command - add support for the ST Electronics M48T35Ax Timekeeper RTC - add support for "flash_real_protect()" for flash chips that provide software sector protection routines, e.g. Intel StrataFlash (board specific code) - add support for LMC and LMG boards; some of the features might be interesting to others: o The flash on these boards is disjointed, e.g. mixed types for different purposes. Therefore it is kept in different memory regions. o The Main Flash is interleaved betweed 2 StrataFlash parts, necessitating some tricks to fit in with PPCBoot. o Real software sector protection is used on the main StrataFlash via flash_real_protect(). The Boot Flash doesn't support software based sector protection. o Specialized code is provided to download 1-6 Xilinx FPGAs. o There is fairly extensive POST testing of some board subsystems. Some of this code could be reused on other targets. The SDRAM bus and RTC battery checks come to mind. --- diff --git a/CHANGELOG b/CHANGELOG index f36606e..277032d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,35 @@ To do: Modifications for 1.1.0: ====================================================================== +* Several patches by Erik Theisen, 14 Oct 2001: +- Fix udelay() for longer delays +- Fix wait_ticks() - don't treat timebase registers as signed +- Fix command name conflicts due to abbreviated length +- Add support for Apple's OS X host environment +- Add support for IBM 4xx DCR registers (commands "getdcr" and + "setdcr" to read and read/modify/write the 4xx DCR) +- Sort command table alphabetically and in descending string length + order to prevent conflicts; added doc/README.commands +- add "reset" option to help info for "date" command +- add support for the ST Electronics M48T35Ax Timekeeper RTC +- add support for "flash_real_protect()" for flash chips that provide + software sector protection routines, e.g. Intel StrataFlash (board + specific code) +- add support for LMC and LMG boards; some of the features might be + interesting to others: + o The flash on these boards is disjointed, e.g. mixed types for + different purposes. Therefore it is kept in different memory + regions. + o The Main Flash is interleaved betweed 2 StrataFlash parts, + necessitating some tricks to fit in with PPCBoot. + o Real software sector protection is used on the main StrataFlash + via flash_real_protect(). The Boot Flash doesn't support software + based sector protection. + o Specialized code is provided to download 1-6 Xilinx FPGAs. + o There is fairly extensive POST testing of some board subsystems. + Some of this code could be reused on other targets. The SDRAM bus + and RTC battery checks come to mind. + * Add support for Fujitsu flash on TQM8260 Patch by Franz Sirl, 19 Oct 2001 diff --git a/MAKEALL b/MAKEALL index d06000b..375a721 100755 --- a/MAKEALL +++ b/MAKEALL @@ -35,6 +35,7 @@ LIST="$LIST \ CPCIISER4 CRAYL1 \ DASA_SIM ERIC \ OCRTC PIP405 \ + W7OLMC W7OLMG \ WALNUT405 \ " diff --git a/Makefile b/Makefile index a6c2f89..a33cfe7 100644 --- a/Makefile +++ b/Makefile @@ -432,6 +432,22 @@ PIP405_config:unconfig echo "CPU = ppc4xx" >>config.mk ; \ echo "#include " >config.h +W7OLMG_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = w7o" >>config.mk ; \ + echo "CPU = ppc4xx" >>config.mk ; \ + echo "#include " >config.h + +W7OLMC_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = w7o" >>config.mk ; \ + echo "CPU = ppc4xx" >>config.mk ; \ + echo "#include " >config.h + WALNUT405_config:unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ diff --git a/README b/README index 8c0d406..ab27123 100644 --- a/README +++ b/README @@ -392,6 +392,7 @@ The following options need to be configured: CFG_CMD_BEDBUG Include BedBug Debugger CFG_CMD_FDC Floppy Disk Support CFG_CMD_SCSI SCSI Support + CFG_CMD_SETGETDCR Support for DCR Register access (4xx only) CFG_CMD_BSP * Board SPecific functions ----------------------------------------------- CFG_CMD_ALL all diff --git a/board/hermes/ppcboot.lds b/board/hermes/ppcboot.lds index c9b31b3..8b28fb1 100644 --- a/board/hermes/ppcboot.lds +++ b/board/hermes/ppcboot.lds @@ -61,7 +61,6 @@ SECTIONS ppc/ppcstring.o (.text) cpu/mpc8xx/interrupts.o (.text) ppc/time.o (.text) - ppc/ticks.o (.text) . = env_offset; common/environment.o(.text) diff --git a/board/w7o/Makefile b/board/w7o/Makefile new file mode 100644 index 0000000..2baa655 --- /dev/null +++ b/board/w7o/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o fpga.o +SOBJS = init.o post1.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/w7o/config.mk b/board/w7o/config.mk new file mode 100644 index 0000000..f402a86 --- /dev/null +++ b/board/w7o/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Wave 7 Optics boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/w7o/error.h b/board/w7o/error.h new file mode 100644 index 0000000..a451da0 --- /dev/null +++ b/board/w7o/error.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ERROR_H_ +#define _ERROR_H_ + +#define ERR_FF 0xff // fault during led test (2) +#define ERR_00 0x00 // fault during led test (2) +#define ERR_LED 0x01 // led test failed (1)(3)(4) +#define ERR_RAMG 0x04 // fault during SDRAM data bus test (2) +#define ERR_RAML 0x05 // SDRAM data bus fault in LSW chip (5) +#define ERR_RAMH 0x06 // SDRAM data bus fault in MSW chip (6) +#define ERR_RAMB 0x07 // SDRAM data bus fault both chips (5)(6)(7) +#define ERR_ADDG 0x08 // fault during Address ghosting test (13) +#define ERR_ADDL 0x09 // +#define ERR_ADDH 0x0a // +#define ERR_ADDB 0x0b // ) +#define ERR_R55G 0x0c // fault during SDRAM fill 55 test (2) +#define ERR_R55L 0x0d // SDRAM fill test 55 failed in LSW chip (8) +#define ERR_R55H 0x0e // SDRAM fill test 55 failed in MSW chip (9) +#define ERR_R55B 0x0f // SDRAM fill test 55 failed in both chips (10) +#define ERR_RAAG 0x10 // fault during SDRAM fill aa test (2) +#define ERR_RAAL 0x11 // SDRAM fill test aa failed in LSW chip (8) +#define ERR_RAAH 0x12 // SDRAM fill test aa failed in MSW chip (9) +#define ERR_RAAB 0x13 // SDRAM fill test aa failed in both chips (10) +#define ERR_R00G 0x14 // fault during SDRAM fill 00 test (2) +#define ERR_R00L 0x15 // SDRAM fill test 00 failed in LSW chip (8) +#define ERR_R00H 0x16 // SDRAM fill test 00 failed in MSW chip (9) +#define ERR_R00B 0x17 // SDRAM fill test 00 failed in both chips (10) +#define ERR_RTCG 0x18 // fault during RTC test +#define ERR_RTCBAT 0x19 // RTC battery failure +#define ERR_RTCVAL 0x20 // RTC not installed or broken +#define ERR_FPGAG 0x21 // fault during FPGA programming +#define ERR_XINIT0 0x22 // Xilinx - INIT line failed to go low +#define ERR_XINIT1 0x23 // Xilinx - INIT line failed to go high +#define ERR_XDONE1 0x24 // Xilinx - DONE line failed to go high +#define ERR_XIMAGE 0x25 // Xilinx - Bad FPGA image in Flash +#define ERR_POSTOK 0x55 // PANIC: psych... OK + +#if !defined(__ASSEMBLY__) +extern void log_stat(int errcode); +extern void log_warn(int errcode); +extern void log_err(int errcode); +#endif + +/* +Debugging suggestions: +(1) periferal data bus shorted or crossed +(2) general processor halt, check reset, watch dog, power supply ripple, processor clock. +(3) check p_we, p_r/w, p_oe, p_rdy lines. +(4) check LED buffers +(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip. +(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip. +(7) check SDRAM control lines and clocks +(8) check decoupling caps, replace LSW SDRAM +(9) check decoupling caps, replace MSW SDRAM +(10) +(11) +(12) +(13) SDRAM address shorted or unconnected, check sdram caps +*/ +#endif /* _ERROR_H_ */ + diff --git a/board/w7o/flash.c b/board/w7o/flash.c new file mode 100644 index 0000000..dcca543 --- /dev/null +++ b/board/w7o/flash.c @@ -0,0 +1,869 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * Based on code by: + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word8(flash_info_t *info, ulong dest, ulong data); +static int write_word32 (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; iflash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("2 x AMD "); break; + case FLASH_MAN_INTEL: printf ("1 x Intel "); break; + default: printf ("Unknown Vendor "); + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf ("AM29LV040 (4096 Kbit, uniform sector size)\n"); + break; + case FLASH_28F320JA3: + printf ("28F320JA3 (32 Mbit = 128K x 32)\n"); + break; + case FLASH_28F640JA3: + printf ("28F640JA3 (64 Mbit = 128K x 64)\n"); + break; + case FLASH_28F128JA3: + printf ("28F128JA3 (128 Mbit = 128K x 128)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + + /* Setup default type */ + info->flash_id = FLASH_UNKNOWN; + info->sector_count =0; + info->size = 0; + + /* Test for Boot Flash */ + if (base == FLASH_BASE0_PRELIM) { + unsigned char value; + volatile unsigned char * addr2 = (unsigned char *)addr; + + /* Write auto select command: read Manufacturer ID */ + *(addr2 + 0x555) = 0xaa; + *(addr2 + 0x2aa) = 0x55; + *(addr2 + 0x555) = 0x90; + + /* Manufacture ID */ + value = *addr2; + switch (value) { + case (unsigned char)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + *addr2 = 0xf0; /* no or unknown flash */ + return 0; + } + + /* Device ID */ + value = *(addr2 + 1); + switch (value) { + case (unsigned char)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + default: + *addr2 = 0xf0; /* => no or unknown flash */ + return 0; + } + } + else { /* MAIN Flash */ + unsigned long value; + volatile unsigned long * addr2 = (unsigned long *)addr; + + /* Write auto select command: read Manufacturer ID */ + *addr2 = 0x90909090; + + /* Manufacture ID */ + value = *addr2; + switch (value) { + case (unsigned long)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + *addr2 = 0xff; /* no or unknown flash */ + return 0; + } + + /* Device ID - This shit is interleaved... */ + value = *(addr2 + 1); + switch (value) { + case (unsigned long)INTEL_ID_28F320JA3: + info->flash_id += FLASH_28F320JA3; + info->sector_count = 32; + info->size = 0x00400000 * 2; + break; /* => 2 X 4 MB */ + case (unsigned long)INTEL_ID_28F640JA3: + info->flash_id += FLASH_28F640JA3; + info->sector_count = 64; + info->size = 0x00800000 * 2; + break; /* => 2 X 8 MB */ + case (unsigned long)INTEL_ID_28F128JA3: + info->flash_id += FLASH_28F128JA3; + info->sector_count = 128; + info->size = 0x01000000 * 2; + break; /* => 2 X 16 MB */ + default: + *addr2 = 0xff; /* => no or unknown flash */ + } + } + + /* Make sure we don't exceed CFG_MAX_FLASH_SECT */ + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + /* set up sector start address table */ + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + break; + case FLASH_28F320JA3: + case FLASH_28F640JA3: + case FLASH_28F128JA3: + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00020000 * 2); /* 2 Banks */ + break; + } + + /* Test for Boot Flash */ + if (base == FLASH_BASE0_PRELIM) { + volatile unsigned char *addr2; + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (AX .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile unsigned char *)(info->start[i]); + info->protect[i] = *(addr2 + 2) & 1; + } + + /* Restore read mode */ + *(unsigned char *)base = 0xF0; /* Reset NORMAL Flash */ + } + else { /* Main Flash */ + volatile unsigned long *addr2; + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (AX .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile unsigned long *)(info->start[i]); + info->protect[i] = *(addr2 + 2) & 0x1; + } + + /* Restore read mode */ + *(unsigned long *)base = 0xFFFFFFFF; /* Reset Flash */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile unsigned char *addr = (unsigned char *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (unsigned char)0x00800080) != (unsigned char)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase8(flash_info_t *info, int s_first, int s_last) +{ + volatile unsigned char *addr = (unsigned char *)(info->start[0]); + volatile unsigned char *addr2; + int flag, prot, sect; + + /* Validate arguments */ + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + /* Check for KNOWN flash type */ + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + /* Check for protected sectors */ + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (unsigned char *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); + + *(addr + 0x555) = (unsigned char)0xAA; + *(addr + 0x2aa) = (unsigned char)0x55; + *(addr + 0x555) = (unsigned char)0x80; + *(addr + 0x555) = (unsigned char)0xAA; + *(addr + 0x2aa) = (unsigned char)0x55; + *addr2 = (unsigned char)0x30; /* sector erase */ + + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (unsigned char *)info->start[0]; + *addr = (unsigned char)0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +int flash_erase32(flash_info_t *info, int s_first, int s_last) +{ + int flag, sect; + ulong start, now, last; + int prot = 0; + + /* Validate arguments */ + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + /* Check for KNOWN flash type */ + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + /* Check for protected sectors */ + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00500050; /* clear status register */ + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* Wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00B000B0; /* suspend erase */ + *addr = 0x00FF00FF; /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + *addr = 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + if (info->start[0] == FLASH_BASE0_PRELIM) + return flash_erase8(info, s_first, s_last); + else + return flash_erase32(info, s_first, s_last); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word + aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word8(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word8(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word8(info, wp, data)); +} + +#define FLASH_WIDTH 4 /* flash bus width in bytes */ +int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; istart[0] == FLASH_BASE0_PRELIM) + retval = write_buff8(info, src, addr, cnt); + else + retval = write_buff32(info, src, addr, cnt); + + return retval; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +static int write_word8(flash_info_t *info, ulong dest, ulong data) +{ + volatile unsigned char *addr2 = (unsigned char *)(info->start[0]); + volatile unsigned char *dest2 = (unsigned char *)dest; + volatile unsigned char *data2 = (unsigned char *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile unsigned char *)dest) & + (unsigned char)data) != (unsigned char)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(unsigned char); i++) + { + *(addr2 + 0x555) = (unsigned char)0xAA; + *(addr2 + 0x2aa) = (unsigned char)0x55; + *(addr2 + 0x555) = (unsigned char)0xA0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (unsigned char)0x80) != + (data2[i] & (unsigned char)0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +static int write_word32(flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = 0x00FF00FF; /* restore read mode */ + + return (0); +} + + +static int _flash_protect(flash_info_t *info, long sector) +{ + int i; + ulong start; + ulong status = 0; + volatile long *addr = (unsigned long *)sector; + + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320JA3: + case FLASH_28F640JA3: + case FLASH_28F128JA3: + *addr = 0x00550055L; /* Clear the status register */ + *addr = 0x00600060L; /* Set lock bit setup */ + *addr = 0x00010001L; /* Set lock bit confirm */ + + /* Wait for command completion */ + start = get_timer (0); + do { + if (get_timer(start) > 1) { /* 75us time out, wait 1ms */ + printf("Protect %x sector TIMEOUT\n", (uint)sector); + *addr = 0x00ff00ffL; /* restore read mode */ + return 0; + } + } while ((*addr & 0x00800080L) != 0x00800080L); + + /* Not successful? */ + status = *addr; + if ((status & ~0x00800080L) != 0x0L) { + printf("Protect %x sector failed: %x\n", + (uint)sector, (uint)status); + *addr = 0x00ff00ffL; + return 0; + } + *addr = 0x00ff00ffL; /* restore read mode */ + break; + case FLASH_AM040: /* No soft sector protection */ + break; + } + + /* Turn protection on for this sector */ + for (i = 0; i < info->sector_count; i++) { + if (info->start[i] == sector) { + info->protect[i] = 1; + break; + } + } + + return 1; +} /* end _flash_protect() */ + +static int _flash_unprotect(flash_info_t *info, long sector) +{ + int i; + ulong start; + ulong status = 0; + volatile long *addr = (unsigned long *)sector; + + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320JA3: + case FLASH_28F640JA3: + case FLASH_28F128JA3: + *addr = 0x00550055L; /* Clear the status register */ + *addr = 0x00600060L; /* Clear lock bit setup */ + *addr = 0x00D000D0L; /* Clear lock bit confirm */ + + /* Wait for command completion */ + start = get_timer (0); + do { + udelay(10000); /* Delay 10ms */ + if (get_timer(start) > 800) {/* 700ms time out, wait 800 */ + printf("Un-protect %x sector TIMEOUT\n", (uint)sector); + *addr = 0x00ff00ffL; /* restore read mode */ + return 0; + } + } while ((*addr & 0x00800080L) != 0x00800080L); + + + /* Not successful? */ + status = *addr; + if ((status & ~0x00800080L) != 0x0L) { + printf("Un-protect %x sector failed: %x\n", + (uint)sector, (uint)status); + *addr = 0x00ff00ffL; + return 0; + } + *addr = 0x00ff00ffL; /* restore read mode */ + break; + case FLASH_AM040: /* No soft sector protection */ + break; + } + + /* + * Fix Intel's little red wagon. Reprotect + * sectors that were protected before we undid + * protection on a specific sector. + */ + for (i = 0; i < info->sector_count; i++) { + if (info->start[i] != sector) { + if (info->protect[i]) + _flash_protect(info, info->start[i]); + } + else /* Turn protection off for this sector */ + info->protect[i] = 0; + } + + return 1; +} /* end _flash_unprotect() */ + + +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retval; + + + if (prot) + retval = _flash_protect(info, sector); + else + retval = _flash_unprotect(info, sector); + + return retval; +} + + + +/*----------------------------------------------------------------------- + */ diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c new file mode 100644 index 0000000..df9f49a --- /dev/null +++ b/board/w7o/fpga.c @@ -0,0 +1,335 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * and + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include "w7o.h" +#include +#include "error.h" + + +static void fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr) +{ + unsigned long i; + volatile unsigned long val; + volatile unsigned short *dest = daddr; /* volatile - bypass optimizer */ + + for (i = 0; i < len; i++, src++) { + val = *src; + *dest = (unsigned short)((val & 0xff000000L) >> 16); + *dest = (unsigned short)((val & 0x00ff0000L) >> 8); + *dest = (unsigned short)(val & 0x0000ff00L); + *dest = (unsigned short)((val & 0x000000ffL) << 8); + } + + /* Terminate programming with 4 C clocks */ + dest = daddr; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + +} + + +int fpgaDownload(unsigned char *saddr, + unsigned long size, + unsigned short *daddr) +{ + int i; /* index, intr disable flag */ + int start; /* timer */ + unsigned long greg, grego; /* GPIO & output register */ + unsigned long length; /* image size in words */ + unsigned long *source; /* image source addr */ + unsigned short *dest; /* destination FPGA addr */ + volatile unsigned short *ndest; /* temp destination FPGA addr */ + volatile unsigned short val; /* temp val */ + unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */ + unsigned long eirq = GPIO_XCV_IRQ; + int retval = -1; /* Function return value */ + + /* Setup some basic values */ + length = (size / 4) + 1; /* size in words, rounding UP + is OK */ + source = (unsigned long *)saddr; + dest = (unsigned short *)daddr; + + /* Get DCR output register */ + grego = in32(IBM405GP_GPIO0_OR); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(IBM405GP_GPIO0_OR, grego); + + /* Setup timeout timer */ + start = get_timer(0); + + /* Wait for FPGA init line */ + while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait for INIT line low */ + /* Check for timeout - 100us max, so use 3ms */ + if (get_timer(start) > 3) { + printf(" failed to start init.\n"); + log_warn(ERR_XINIT0); /* Don't halt */ + + /* Reset line stays low */ + goto done; /* I like gotos... */ + } + } + + /* Unreset FPGA */ + grego |= GPIO_XCV_PROG; /* PROG line high */ + out32(IBM405GP_GPIO0_OR, grego); + + /* Wait for FPGA end of init period . */ + while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT line hi */ + + /* Check for timeout */ + if (get_timer(start) > 3) { + printf(" failed to exit init.\n"); + log_warn(ERR_XINIT1); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(IBM405GP_GPIO0_OR, grego); + + goto done; + } + } + + /* Now program FPGA ... */ + ndest = dest; + for (i = 0; i < CONFIG_NUM_FPGAS; i++) { + /* Toggle IRQ/GPIO */ + greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ + greg |= eirq; /* toggle irq/gpio */ + mtdcr(CPC0_CR0, greg); /* ... just do it */ + + /* turn on open drain for CNFG */ + greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */ + greg |= cnfg; /* CNFG open drain */ + out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */ + + /* Turn output enable on for CNFG */ + greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */ + greg |= cnfg; /* CNFG tristate inactive */ + out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */ + + /* Setup FPGA for programming */ + grego &= ~cnfg; /* CONFIG line low */ + out32(IBM405GP_GPIO0_OR, grego); + + /* + * Program the FPGA + */ + printf("\n destination: 0x%lx ", (unsigned long)ndest); + + fpga_img_write(source, length, (unsigned short *)ndest); + + /* Done programming */ + grego |= cnfg; /* CONFIG line high */ + out32(IBM405GP_GPIO0_OR, grego); + + /* Turn output enable OFF for CNFG */ + greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */ + greg &= ~cnfg; /* CNFG tristate inactive */ + out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */ + + /* Toggle IRQ/GPIO */ + greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ + greg &= ~eirq; /* toggle irq/gpio */ + mtdcr(CPC0_CR0, greg); /* ... just do it */ + + ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */ + cnfg >>= 1; /* XXX - Next */ + eirq >>= 1; + } + + /* Terminate programming with 4 C clocks */ + ndest = dest; + for (i = 0; i < CONFIG_NUM_FPGAS; i++) { + val = *ndest; + val = *ndest; + val = *ndest; + val = *ndest; + ndest = (unsigned short *)((char *)ndest + 0x00100000L); + } + + /* Setup timer */ + start = get_timer(0); + + /* Wait for FPGA end of programming period . */ + while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE line low */ + + /* Check for timeout */ + if (get_timer(start) > 3) { + printf(" done failed to come high.\n"); + log_warn(ERR_XDONE1); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(IBM405GP_GPIO0_OR, grego); + + goto done; + } + } + + printf("\n FPGA load succeeded.\n"); + retval = 0; /* Program OK */ + +done: + + return retval; +} + +/* FPGA image is stored in flash */ +extern flash_info_t flash_info[]; + +int init_fpga(void) +{ + unsigned int i,j,ptr; // these are general purpose + unsigned char bufchar; // general purpose charactor + unsigned char *buf; // start of image pointer + unsigned long len; // length of image + unsigned char *fn_buf; // start of file name string + unsigned int fn_len; // length of file name string + unsigned char *xcv_buf; // pointer to start of fpga bit file image + unsigned long xcv_len; // length of fpga bit file image + unsigned long crc; // 30bit crc stored in image + unsigned long calc_crc; // 30bit crc calculated from image + int retval = -1; + + /* Tell the world what we are doing */ + printf("FPGA: "); + + /* + * Get address of first sector where the FPGA + * image is stored. + */ + buf = (unsigned char *)flash_info[1].start[0]; + + /* + * Get the stored image's CRC & length. + */ + crc = *(unsigned long *)(buf+4); /* CRC is first long word */ + len = *(unsigned long *)(buf+8); /* Cimage len is next long word */ + + /* Pedantic */ + if ((len < 0x133A4) || (len > 0x80000)) + goto bad_image; + + /* + * Get the file name pointer and length. + */ + + fn_len = (*(unsigned short *)(buf+12) & 0xff);/* filename length + is next short */ + fn_buf = buf + 14; + + /* + * Get the FPGA image pointer and length length. + */ + + xcv_buf = fn_buf + fn_len; /* pointer to fpga image */ + xcv_len = len - 14 - fn_len; /* fpga image length */ + + /* Check for uninitialized FLASH */ + if ((strncmp(buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0)) + goto bad_image; + + /* + * Calculate and Check the image's CRC. + */ + calc_crc = crc32(0, xcv_buf, xcv_len); + if (crc != calc_crc) { + printf("\nfailed - bad CRC\n"); + goto done; + } + + /* output the file name */ + printf("file name : "); + for (i=0;i'~') bufchar = '.'; + putc(bufchar); + } + + /* + * find rest of display data + */ + ptr = 15; // offset to ncd filename length in fpga image + j= xcv_buf[ptr]; // get length of ncd filename + if (j>32) goto bad_image; + ptr=ptr+j+3; // skip ncd filename string + 3 bytes more bytes + /* + * output target device string + */ + j= xcv_buf[ptr++]-1; // length of target string less terminator + if (j>32) goto bad_image; + printf("\n target : "); + for (i=0;i'~') bufchar = '.'; + putc(bufchar); + } + /* + * output compilation date string and time string + */ + ptr+=3; // skip two bytes of unknown meaning + printf("\n synth time : "); + j=(xcv_buf[ptr++] - 1); // length of date string less terminator + if (j>32) goto bad_image; + for (i=0;i'~') bufchar = '.'; + putc(bufchar); + } + ptr+=3; // skip two bytes of unknown meaning + printf(" - "); + j=(xcv_buf[ptr++] - 1); // slen = targ dev string length + if (j>32) goto bad_image; + for (i=0;i'~') bufchar = '.'; + putc(bufchar); + } + /* + * output crc and length strings + */ + printf("\n len & crc : 0x%lx 0x%lx",len,crc); + + + /* + * Program the FPGA. + */ + retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len, + (unsigned short *)0xfd000000L); + return retval; + +bad_image: + printf("\n BAD FPGA image format @ %lx\n", flash_info[1].start[0]); + log_warn(ERR_XIMAGE); +done: + return retval; +} + diff --git a/board/w7o/init.S b/board/w7o/init.S new file mode 100644 index 0000000..f23ee62 --- /dev/null +++ b/board/w7o/init.S @@ -0,0 +1,387 @@ +//------------------------------------------------------------------------------+ +// +// This source code has been made available to you by IBM on an AS-IS +// basis. Anyone receiving this source is licensed under IBM +// copyrights to use it in any way he or she deems fit, including +// copying it, modifying it, compiling it, and redistributing it either +// with or without modifications. No license under IBM patents or +// patent applications is to be implied by the copyright license. +// +// Any user of this software should understand that IBM cannot provide +// technical support for this software and will not be responsible for +// any consequences resulting from the use of this software. +// +// Any person who transfers this source code or any derivative work +// must include the IBM copyright notice, this paragraph, and the +// preceding two paragraphs in the transferred software. +// +// COPYRIGHT I B M CORPORATION 1995 +// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +//------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Function: ext_bus_cntlr_init +// Description: Initializes the External Bus Controller for the external +// peripherals. IMPORTANT: For pass1 this code must run from +// cache since you can not reliably change a peripheral banks +// timing register (pbxap) while running code from that bank. +// For ex., since we are running from ROM on bank 0, we can NOT +// execute the code that modifies bank 0 timings from ROM, so +// we run it from cache. +// Bank 0 - Flash bank 0 +// Bank 1 - CAN0, CAN1, CAN2, CAN3 +// Bank 2 - Expansion Bus +// Bank 3 - 16552 +// Bank 4 - FPGA internal (ADC, DAC, etc.) +// Bank 5 - Flash bank 1 (dummy) +//----------------------------------------------------------------------------- +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + + .globl tmp_stack_init + .globl ext_bus_cntlr_init + .globl sdram_test + .extern sramTest + +tmp_stack_init: + // set up stack + addis r1, 0, 0xfc00 // set stack (R1) to top of on chip memory + // so we can use it as stack + // set up 1st dummy frame to store stack under flow vector ( fake return addr) + stwu r1, -8(r1) // Save back chain and move SP + // set up 2nd dummy frame to store called function's return address + addis r3, 0, 0xffff // set 1st link register to reset vector + ori r3, r3, 0xfffc // so underflow resets everything + stwu r1, -8(r1) // Save back chain and move SP + stw r3, +12(r1) // Save link register (underflow vect) + blr // return, were done + +ext_bus_cntlr_init: + mflr r4 // save link register + bl ..getAddr +..getAddr: + mflr r3 // get address of ..getAddr + mtlr r4 // restore link register + addi r4,0,14 // set ctr to 14; used to prefetch + mtctr r4 // 14 cache lines to fit this function + // in cache (gives us 8x10=80 instrctns) +..ebcloop: + icbt r0,r3 // prefetch cache line for addr in r3 + addi r3,r3,32 // move to next cache line + bdnz ..ebcloop // continue for 10 cache lines + + //------------------------------------------------------------------- + // Delay to ensure all accesses to ROM are complete before changing + // bank 0 timings. 200usec should be enough. + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp: + bdnz ..spinlp // spin loop + + //----------------------------------------------------------------------- + // Memory Bank 0 (Flash Bank 0) initialization + //----------------------------------------------------------------------- + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x0305 // BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0, + ori r4,r4,0x0440 // TH=2,RE=0,SOR=0,BEM=1,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFE3 // BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0(8 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 1 (Flash Bank 1) initialization (dummy for flash_init only!!!) + //----------------------------------------------------------------------- + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,0x0385 // BME=0,TWT=7,CSN=1,OEN=1,WBN=0,WBF=0, + ori r4,r4,0x0240 // TH=1,RE=0,SOR=0,BEM=1,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0xF00F // BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W), + ori r4,r4,0xC000 // BW=0x10(32 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 2 RTC/NVRAM initialization + //----------------------------------------------------------------------- + addi r4,0,pb2ap + mtdcr ebccfga,r4 + addis r4,0,0x0280 // BME=0,TWT=5,CSN=0,OEN=0,WBN=0,WBF=0, + ori r4,r4,0x0240 // TH=1,RE=0,SOR=0,BEM=1,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb2cr + mtdcr ebccfga,r4 + addis r4,0,0xFC01 // BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0(8 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 3 Core/Gateway FPGA 0 + //----------------------------------------------------------------------- + addi r4,0,pb3ap + mtdcr ebccfga,r4 + addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0, + ori r4,r4,0x0400 // TH=2,RE=0,SOR=0,BEM=0,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb3cr + mtdcr ebccfga,r4 + addis r4,0,0xFD01 // BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xA000 // BW=0x1(16 bits) + mtdcr ebccfgd,r4 + +/// Core CS configuration +#ifdef CONFIG_W7OLMC + //----------------------------------------------------------------------- + // Memory Bank 4 Core FPGA 1 + //----------------------------------------------------------------------- + addi r4,0,pb4ap + mtdcr ebccfga,r4 + addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0, + ori r4,r4,0x0400 // TW=2,RE=0,SOR=0,BEM=0,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,0xFD11 // BAS=0xFD1,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xA000 // BW=0x1(16 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 5 Core FPGA 2 + //----------------------------------------------------------------------- + addi r4,0,pb5ap + mtdcr ebccfga,r4 + addis r4,0,0x0200 // BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0, + ori r4,r4,0x0400 // TW=2,RE=0,SOR=0,BEM=0,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,0xFD21 // BAS=0xFD2,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xA000 // BW=0x1(16 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 6 Core Not Used + //----------------------------------------------------------------------- + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 +// Gateway Configuration +#elif defined(CONFIG_W7OLMG) + //----------------------------------------------------------------------- + // SAM - Change PCIINT signal to PerWE + //----------------------------------------------------------------------- + mfdcr r4, 0xB2 + ori r4, r4, 0x4000 + mtdcr 0xB2, r4 + + //----------------------------------------------------------------------- + // Memory Bank 4 SAM 8-bit + //----------------------------------------------------------------------- + addi r4,0,pb4ap + mtdcr ebccfga,r4 // FIXME Comment + addis r4,0,0x0284 + ori r4,r4,0x0380 + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,0xFE87 + ori r4,r4,0x8000 + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Memory Bank 5 SAM 16-bit + //----------------------------------------------------------------------- + addi r4,0,pb5ap + mtdcr ebccfga,r4 // FIXME Comment + addis r4,0,0x0284 + ori r4,r4,0x0380 + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,0xFD87 + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + //----------------------------------------------------------------------- + // Memory Bank 6 Not used - + //----------------------------------------------------------------------- + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 +#else +# error "Unknown W7O board configuration" +#endif + + //----------------------------------------------------------------------- + // Memory Bank 7 LEDs + //----------------------------------------------------------------------- + addi r4,0,pb7ap + mtdcr ebccfga,r4 + addis r4,0,0x0305 // BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0, + ori r4,r4,0x0440 // TH=2,RE=0,SOR=0,BEM=1,PEN=0 + mtdcr ebccfgd,r4 + + addi r4,0,pb7cr + mtdcr ebccfga,r4 + addis r4,0,0xFE01 // BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0xC000 // BW=0x2(32 bits) + mtdcr ebccfgd,r4 + + //----------------------------------------------------------------------- + // Setup OCM + //----------------------------------------------------------------------- + addis r4, 0, 0xf800 // OCM @ 0xf8000000 + mtdcr 0x1a, r4 + addis r4, 0, 0xC000 // OCM enabled + mtdcr 0x1b, r4 + +fugu: + mflr r31 // Save SP + bl tmp_stack_init // setup temporary stack + bl kick_dog // Reset the watchdog + mtlr r31 // Resort link register + blr // Return to calling function + +//----------------------------------------------------------------------------- +// Function: sdram_init +// Description: Configures SDRAM memory banks. +// Auto Memory Configuration option reads the SDRAM EEPROM +// via the IIC bus and then configures the SDRAM memory +// banks appropriately. If Auto Memory Configuration is +// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is +// plugged, ie. the DIMM that shipped wih the Eval board. +//----------------------------------------------------------------------------- + .globl sdram_init + +sdram_init: + + mflr r31 + + //------------------------------------------------------------------- + // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) + //------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0008 + ori r4,r4,0x4001 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. + // To set the appropriate timings, we need to know the SDRAM speed. + // We can use the PLB speed since the SDRAM speed is the same as + // the PLB speed. The PLB speed is the FBK divider times the + // 405GP reference clock, which on the Walnut board is 33Mhz. + // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is + // 100Mhz; if FBK is 3, SDRAM is 133Mhz. + // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and + // maybe 133Mhz. + //------------------------------------------------------------------- + mfdcr r5,strap // determine FBK divider + // via STRAP reg to calc PLB speed. + // SDRAM speed is the same as the PLB + // speed. + rlwinm r4,r5,4,0x3 // get FBK divide bits + +..chk_66: + cmpi %cr0,0,r4,0x1 + bne ..chk_100 + addis r6,0,0x0085 // SDTR1 value for 66Mhz + ori r6,r6,0x4005 + addis r7,0,0x03F8 // RTR value for 66Mhz + b ..sdram_ok +..chk_100: + cmpi %cr0,0,r4,0x2 + bne ..chk_133 + addis r6,0,0x0086 // SDTR1 value for 100Mhz + ori r6,r6,0x400D + addis r7,0,0x05F0 // RTR value for 100Mhz + b ..sdram_ok +..chk_133: + addis r6,0,0x0107 // SDTR1 value for 133Mhz + ori r6,r6,0x4015 + addis r7,0,0x07F0 // RTR value for 133Mhz + +..sdram_ok: + //------------------------------------------------------------------- + // Set SDTR1 + //------------------------------------------------------------------- + addi r4,0,mem_sdtr1 + mtdcr memcfga,r4 + mtdcr memcfgd,r6 + + //------------------------------------------------------------------- + // Set RTR + //------------------------------------------------------------------- + addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + //------------------------------------------------------------------- + // Delay to ensure 200usec have elapsed since reset. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0000 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp2: + bdnz ..spinlp2 // spin loop + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Delay to ensure 10msec have elapsed since reset. This is + // required for the MPC952 to stabalize. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles + // This delay should occur before accessing SDRAM. + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp3: + bdnz ..spinlp3 // spin loop + + bl kick_dog // Reset the watchdog + bl test_led // test the LEDs + bl test_sdram // test the dram + mtlr r31 + blr + diff --git a/board/w7o/post1.S b/board/w7o/post1.S new file mode 100644 index 0000000..bd3d12e --- /dev/null +++ b/board/w7o/post1.S @@ -0,0 +1,398 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * and + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +// +//Description: +// Routine to exercise memory for the bringing up of our boards. +// +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#include "error.h" + +#define _ASMLANGUAGE + + .globl test_sdram + .globl test_led + .globl log_stat + .globl log_warn + .globl log_err + +//**************************************** +//**************************************** +//******** LED register test ******** +//**************************************** +//**************************************** +test_led: + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -8(r1) // Save back chain and move SP + stw r0, +12(r1) // Save link register + +#if defined(CONFIG_W7OLMG) + addi r3, 0, ERR_FF // first test value is ffff + addi r4, r3, 0 // save copy of pattern + bl set_led // store first test value + bl get_led // read it back + xor. r4, r4, r3 // compare to original + beq LED2 // next test + addi r3, 0, ERR_LED // error code = 1 + bl log_err // display error and halt +LED2: addi r3, 0, ERR_00 // 2nd test value is 0000 + addi r4, r3, 0 // save copy of pattern + bl set_led // store first test value + bl get_led // read it back + xor. r4, r4, r3 // compare to original + beq LED3 // next test + addi r3, 0, ERR_LED // error code = 1 + bl log_err // display error and halt +#endif +LED3: /* restore stack and return */ + lwz r0, +12(r1) // Get saved link register + mtlr r0 // Restore link register + addi r1, r1, +8 // Remove frame from stack + blr // Return to calling function + + +//**************************************** +//**************************************** +//******** SDRAM TESTS ******** +//**************************************** +//**************************************** +test_sdram: + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -8(r1) // Save back chain and move SP + stw r0, +12(r1) // Save link register + +//**************************************** +//******** sdram data bus test ******** +//**************************************** + // set up led register for this test +Data_Buster: + addi r3, 0, ERR_RAMG // set led code to 1 + bl log_stat // store test value + //now test the dram data bus + xor r7, r7, r7 // load r7 with 0 + xor r6, r6, r6 // load r6 with base address of sdram + addis r5, 0, 0x5555 // load r4 with test value + ori r5, r5, 0x5555 + stw r5,0(r6) // sto the value + lwz r3,0(r6) // read it back + xor r3,r3,r5 // compare it to original + addis r5, 0, 0xaaaa // load r4 with test value + ori r5, r5, 0xaaaa + stw r5,0(r6) // sto the value + lwz r4,0(r6) // read it back + xor r4,r4,r5 // compare it to original + or r3,r3,r4 // or together both error terms + // now that we have the error bits, we have to decide which part they are in + bl get_idx // r5 is now index to error + addi r3, r3, ERR_RAMG + cmpwi r3, ERR_RAMG // check for errors + beq db2 // skip if no errors + bl log_err // log the error +db2: b Ghost_Buster // on to next test + + +//**************************************************** +//******** test for address ghosting in dram ******** +//**************************************************** + +Ghost_Buster: + addi r3, 0, ERR_ADDG // set the leds for address ghost test + bl set_led + addi r7, 0, 0x00ff // r7 = one byte of set bits + addi r8, 0, 0 // r8 = 0 for testing + addi r9, 0, 1 // r9 = 1 this is shifted to get ghost addresses + addi r6, 0, 0 // r6 is main referance loop counter, 0 to 23 + // r5 is ghost loop counter, 0 to 22 + // r4 is referance address + // r3 is ghost address + + // first fill memory with zeros + addis r4, 0, 0x0100 // cover 8M of longs + mtctr r4 // setup base address + addi r4, 0, 0 // r4 is address, start at 0 +0: stw r8, 0(r4) // Store zero value + addi r4, r4, 4 // Increment to next word + bdnz 0b // Round and round... + + // now do main test +outside: + // Calculate the referance address + // the referance address is calculated by setting the (r6-1)bit of the base address + // when r6=0, the referance address is the base address. + // setting the bit is done with the following shift functions. + slw r4,r9,r6 // tmp = 1 << i + srwi r4,r4,1 // tmp = tmp >> 1 + + // fill referance address with Fs + stb r7,0(r4) + + // ghost (inner) loop, now check all posible ghosted addresses + addi r5, 0, 0 // r5 is the ghosted loop counter,0 to 22 +inside: + // Calculate the ghost address + // the ghost address is calculated by toggling the r6th bit of the referance address + slw r3, r9, r5 // r3 = bit pattern, only r5th bit is set + xor r3, r4, r3 // r3 = ghost address = ref addr with r5th bit flipped + + // now check for ghosting + lbz r3,0(r3) // get contents + cmpwi r3, 0 // compare read value to 0 + bne Casper // we found a ghost! + + // now close ghost ( inner ) loop + addi r5, r5, 1 // increment inner loop counter + cmpwi r5, 23 // check for last inner loop + ble inside // do more inner loops + + // now close referance ( outer ) loop + stb r8, 0(r4) // zero out the altered address loc. + addi r6, r6, 1 // increment outer loop counter + cmpwi r6, 24 // check for last inner loop + ble outside // do more outer loops + + // were done, lets go home + b Bit_Buster +Casper: addi r3, 0, ERR_ADDG // get indexed error message + b log_err // output led error code, halt everything + +//**************************************************** +//******** SDRAM data fill tests ********** +//**************************************************** +Bit_Buster: + addis r5, 0, 0x0400 // FIXME - hard coded @ 64MB 0x04000000 + + // Test 55555555 + addi r3, 0, ERR_R55G // set up error code in case we fail + bl log_stat // store test value + addis r4, 0, 0x5555 + ori r4, r4, 0x5555 + bl fill_test + + // Test aaaaaaaa + addi r3, 0, ERR_RAAG // set up error code in case we fail + bl log_stat // store test value + addis r4, 0, 0xAAAA + ori r4, r4, 0xAAAA + bl fill_test + + // Test 00000000 + addi r3, 0, ERR_R00G // set up error code in case we fail + bl log_stat // store test value + addis r4, 0, 0 + ori r4, r4, 0 + bl fill_test + + +//**************************************************** +//******** finished these tests ********** +//**************************************************** + /* restore stack and return */ + lwz r0, +12(r1) // Get saved link register + mtlr r0 // Restore link register + addi r1, r1, +8 // Remove frame from stack + blr // Return to calling function + + + +//**************************************************** +//******** fill test ******** +//**************************************************** +// tests memory by filling with value, and reading back +// r5 = Size of memory in bytes +// r4 = Value to write +// r3 = Error code +fill_test: + mflr r30 + bl kick_dog // Reset the watchdog + // first fill memory with Value + srawi r7, r5, 2 // convert bytes to longs + mtctr r7 // setup counter + addi r6, 0, 0 // Make r6 = addr 0 +0: stw r4, 0(r6) // Store value + addi r6, r6, 4 // Increment to next word + bdnz 0b // Round and round... + + bl kick_dog // Reset the watchdog + + // now confirm Value is in memory + mtctr r7 // setup counter + addi r6, 0, 0 // Make r6 = addr 0 +0: lwz r7, 0(r6) // get value from memory + xor. r7, r7, r4 // Writen = Read ? + bne ft_err // If bad, than halt +2: addi r6, r6, 4 // Increment to next word + bdnz 0b // Round and round... + + bl kick_dog // Reset the watchdog + mtlr r30 + blr // return + +ft_err: addi r7, r3, 0 // save current led code + addi r3, r7, 0 // get pattern in r3 + bl get_idx // get index from r3 + add r3, r3, r4 // add index to old led code + bl log_err // output led error code, halt everything + + +//**************************************************** +//******* get error index from r3 pattern ******** +//**************************************************** +get_idx: // r4 = (MSW(r3) !=0)*2 + (LSW(r3) !=0) + andi. r4, r3, 0xffff // check for lower bits + beq gi2 // skip if no bits set + andis. r4, r3, 0xffff // check for upper bits + beq gi3 // skip if no bits set + addi r4, 0, 3 // both upper and lower bits set + blr +gi2: andis. r4, r3, 0xffff // check for upper bits + beq gi4 // skip if no bits set + addi r4, 0, 2 // only upper bits set + blr +gi3: addi r4, 0, 1 // only lower bits set + blr +gi4: addi r4, 0, 0 // no bits set + blr + +//**************************************************** +//******** set LED to R5 and hang ******** +//**************************************************** +log_stat: // output a led code and continue +set_led: + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -12(r1) // Save back chain and move SP + stw r0, +16(r1) // Save link register + stw r4, +8(r1) // save R4 + + addis r4, 0, 0xfe00 // LED buffer is at 0xfe000000 + xori r3,r3, 0xffff // complement led code since active low + sth r3, 0(r4) // store first test value + xori r3,r3, 0xffff // complement led code since active low + + /* restore stack and return */ + lwz r0, +16(r1) // Get saved link register + mtlr r0 // Restore link register + lwz r4, +8(r1) // restore r4 + addi r1, r1, +12 // Remove frame from stack + blr // Return to calling function + +get_led: + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -12(r1) // Save back chain and move SP + stw r0, +16(r1) // Save link register + stw r4, +8(r1) // save R4 + + addis r4, 0, 0xfe00 // LED buffer is at 0xfe000000 + lhz r3, 0(r4) // store first test value + xori r3,r3, 0xffff // complement led code since active low + + /* restore stack and return */ + lwz r0, +16(r1) // Get saved link register + mtlr r0 // Restore link register + lwz r4, +8(r1) // restore r4 + addi r1, r1, +12 // Remove frame from stack + blr // Return to calling function + +log_err: // output the error and hang the board ( for now ) + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -8(r1) // Save back chain and move SP + stw r0, +12(r1) // Save link register + bl set_led +halt: + b halt // hang + + /* restore stack and return */ + lwz r0, +12(r1) // Get saved link register + mtlr r0 // Restore link register + addi r1, r1, +8 // Remove frame from stack + blr // Return to calling function + +log_warn: // output a warning, then continue with operations + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -8(r1) // Save back chain and move SP + stw r0, +12(r1) // Save link register + + bl set_led // set the led pattern + addis r3, 0, 0xf // r3 = 0xf4240 = 1e6 + ori r3, r3, 0x4240 + xor r4,r4,r4 // r4 = 0 + bl udelay // delay 1e6 usec = 1 sec + + /* restore stack and return */ + lwz r0, +12(r1) // Get saved link register + mtlr r0 // Restore link register + addi r1, r1, +8 // Remove frame from stack + blr // Return to calling function + +//**************************************************** +//******** void kick_dog(void) ******** +//******** Toggle the watchdog line ******** +//**************************************************** + .section ".text" + .globl kick_dog + .align 2 + .type kick_dog, @function +kick_dog: + /* save the return info on stack */ + mflr r0 // Get link register + stwu r1, -16(r1) // Save back chain and move SP + stw r0, +20(r1) // Save link register + + /* Save r3/r4 since we might be called from asm */ + stw r4, +8(r1) + stw r3, +12(r1) + + addis r4, 0, 0xfe00 // LED register is at 0xfe000000 + + lhz r3, 0(r4) // Read register + xori r3, r3, 0x8000 // Toggle watchdog bit + sth r3, 0(r4) + + /* Restore r3/r4 */ + lwz r3, +12(r1) + lwz r4, +8(r1) + + /* restore stack and return */ + lwz r0, +20(r1) // Get saved link register + mtlr r0 // Restore link register + addi r1, r1, +16 // Remove frame from stack + blr // Return to calling function +// end kick_dog() + + diff --git a/board/w7o/ppcboot.lds b/board/w7o/ppcboot.lds new file mode 100644 index 0000000..be5b358 --- /dev/null +++ b/board/w7o/ppcboot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/w7o/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + ppc/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/w7o/ppcboot.lds.debug b/board/w7o/ppcboot.lds.debug new file mode 100644 index 0000000..266238e --- /dev/null +++ b/board/w7o/ppcboot.lds.debug @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c new file mode 100644 index 0000000..e8c4579 --- /dev/null +++ b/board/w7o/w7o.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "w7o.h" +#include +#include "error.h" + + +/* ------------------------------------------------------------------------- */ + +extern int init_fpga(void); + +int board_pre_init (void) +{ +#if defined(CONFIG_W7OLMG) + /* + * Setup GPIO pins - reset devices. + */ + out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ + out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ + out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive + * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive + * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive + * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive + * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive + * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + +#elif defined(CONFIG_W7OLMC) + /* + * Setup GPIO pins + */ + out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ + out32(IBM405GP_GPIO0_OR, 0x01800000); /* set output pins to default */ + out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive + * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive + * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + +#else /* Unknown */ +# error "Unknown W7O board configuration" +#endif + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char *s = getenv("serial#"); + unsigned char *e; +#if 0 + int i; + int index; + int len; +#endif + + if (!s || strncmp(s, "LMC", 3) || strncmp(s, "LMG", 3)) + { + printf ("### No HW ID - assuming NOTHING\n"); + } + else + { + for (e=s; *e; ++e) { + if (*e == ' ') + break; + } + + for ( ; s + +/* IBM 405GP PowerPC GPIO registers */ +#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */ +#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ +#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ +#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ + +/* IBM 405GP DCRs */ +#define CPC0_CR0 0xb1 /* Chip control register 0 */ + +/* LMG FPGA <=> CPU GPIO signals */ +#define LMG_XCV_INIT 0x10000000L +#define LMG_XCV_PROG 0x04000000L +#define LMG_XCV_DONE 0x00400000L +#define LMG_XCV_CNFG_0 0x08000000L +#define LMG_XCV_IRQ_0 0x0L + +/* LMC FPGA <=> CPU GPIO signals */ +#define LMC_XCV_INIT 0x00800000L +#define LMC_XCV_PROG 0x40000000L +#define LMC_XCV_DONE 0x01000000L +#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */ +#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */ +#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */ +#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */ +#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */ +#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */ + + +/* + * Setup FPGA <=> GPIO mappings + */ +#if defined(CONFIG_W7OLMG) +# define GPIO_XCV_INIT LMG_XCV_INIT +# define GPIO_XCV_PROG LMG_XCV_PROG +# define GPIO_XCV_DONE LMG_XCV_DONE +# define GPIO_XCV_CNFG LMG_XCV_CNFG_0 +# define GPIO_XCV_IRQ LMG_XCV_IRQ_0 +# define GPIO_GPIO_1 0x40000000L +# define GPIO_GPIO_6 0x02000000L +# define GPIO_GPIO_7 0x01000000L +# define GPIO_GPIO_8 0x00800000L +#elif defined(CONFIG_W7OLMC) +# define GPIO_XCV_INIT LMC_XCV_INIT +# define GPIO_XCV_PROG LMC_XCV_PROG +# define GPIO_XCV_DONE LMC_XCV_DONE +# define GPIO_XCV_CNFG LMC_XCV_CNFG_0 +# define GPIO_XCV_IRQ LMC_XCV_IRQ_0 +#else +# error "Unknown W7O board configuration" +#endif + +#endif /* _W7O_H_ */ + diff --git a/common/Makefile b/common/Makefile index 7526f4a..10d77fa 100644 --- a/common/Makefile +++ b/common/Makefile @@ -26,16 +26,18 @@ include $(TOPDIR)/config.mk LIB = libcommon.a AOBJS = environment.o -COBJS = board.o main.o command.o \ - cmd_boot.o cmd_bootm.o cmd_cache.o \ - cmd_console.o cmd_date.o cmd_eeprom.o \ - cmd_flash.o cmd_ide.o cmd_mem.o cmd_net.o \ - cmd_nvedit.o cmd_pcmcia.o cmd_reginfo.o \ - cmd_fdc.o cmd_scsi.o cmd_autoscript.o \ - cmd_bedbug.o bedbug.o s_record.o dlmalloc.o \ - kgdb.o console.o lists.o devices.o flash.o cmd_i2c.o \ - cmd_immap.o miiphyutil.o miiphybb.o cmd_mii.o \ - hush.o +COBJS = board.o main.o command.o bedbug.o \ + cmd_autoscript.o cmd_bedbug.o cmd_boot.o \ + cmd_bootm.o cmd_cache.o cmd_console.o \ + cmd_date.o cmd_dcr.o cmd_eeprom.o \ + cmd_fdc.o cmd_flash.o cmd_i2c.o \ + cmd_ide.o cmd_immap.o cmd_mem.o \ + cmd_mii.o cmd_net.o cmd_nvedit.o \ + cmd_pcmcia.o cmd_reginfo.o cmd_scsi.o \ + console.o devices.o dlmalloc.o \ + flash.o hush.o kgdb.o \ + lists.o miiphybb.o miiphyutil.o \ + s_record.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/board.c b/common/board.c index 21c99e9..8c9c581 100644 --- a/common/board.c +++ b/common/board.c @@ -165,7 +165,8 @@ board_init_f (ulong bootflag) defined(CONFIG_OCRTC) || \ defined(CONFIG_PIP405) || \ defined(CONFIG_RPXSUPER) || \ - defined(CONFIG_WALNUT405) + defined(CONFIG_WALNUT405) || \ + defined(CONFIG_W7O) board_pre_init(); /* very early board init code (fpga boot, etc.) */ #endif @@ -248,7 +249,8 @@ board_init_f (ulong bootflag) #endif /* CONFIG_WATCHDOG */ #if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \ - defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) + defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \ + defined(CONFIG_W7O) /* miscellaneous platform dependent initialisations */ if (misc_init_f() < 0) { puts (failed); @@ -610,6 +612,7 @@ void board_init_r (bd_t *bd, ulong dest_addr) defined(CONFIG_HYMOD) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_PCU_E) || \ + defined(CONFIG_W7O) || \ defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ misc_init_r(bd); diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c new file mode 100644 index 0000000..88cea41 --- /dev/null +++ b/common/cmd_dcr.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * IBM 4XX DCR Functions + */ + +#include +#include +#include +#include + +#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) + +/* ====================================================================== + * Interpreter command to retrieve an IBM PPC 4xx Device Control Register + * ====================================================================== + */ +int do_getdcr( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] ) +{ + unsigned short dcrn; /* Device Control Register Num */ + unsigned long value; /* DCR's value */ + + /* Validate arguments */ + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Get a DCR */ + dcrn = (unsigned short)simple_strtoul(argv[ 1 ], NULL, 16); + value = get_dcr(dcrn); + + printf("%04x: %08lx\n", dcrn, value); + + return 0; +} /* do_getdcr */ + + +/* ====================================================================== + * Interpreter command to set an IBM PPC 4xx Device Control Register + * ====================================================================== +*/ +int do_setdcr(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + unsigned short dcrn; /* Device Control Register Num */ + unsigned long value; /* DCR's value */ + int nbytes; + extern char console_buffer[]; + + /* Validate arguments */ + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Set a DCR */ + dcrn = (unsigned short)simple_strtoul(argv[1], NULL, 16); + do { + value = get_dcr(dcrn); + printf("%04x: %08lx", dcrn, value); + nbytes = readline(" ? "); + if (nbytes == 0) { + /* + * pressed as only input, don't modify current + * location and exit command. + */ + nbytes = 1; + return 0; + } else { + unsigned long i; + char *endp; + i = simple_strtoul(console_buffer, &endp, 16); + nbytes = endp - console_buffer; + if (nbytes) + set_dcr(dcrn, i); + } + } while (nbytes); + + return 0; +} /* do_setdcr */ + +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 3f8a1ed..8d17504 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -27,6 +27,7 @@ #include #include #include +#include #if (CONFIG_COMMANDS & CFG_CMD_FLASH) @@ -267,10 +268,15 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) p ? "" : "Un-", bank); for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, info->start[i], p)) + rcode = 1; +#else info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ } } - return 0; + return rcode; } if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) { @@ -282,9 +288,14 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) p ? "" : "Un-", sect_first, sect_last, (info-flash_info)+1); for (i = sect_first; i <= sect_last; i++) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, info->start[i], p)) + rcode = 1; +#else info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ } - return 0; + return rcode; } if (argc != 4) { @@ -308,9 +319,14 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) return 1; } for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, info->start[i], p)) + rcode = 1; +#else info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ } - return 0; + return rcode; } addr_first = simple_strtoul(argv[2], NULL, 16); @@ -369,7 +385,12 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) if (s_first>=0 && s_first<=s_last) { protected += s_last - s_first + 1; for (i=s_first; i<=s_last; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, info->start[i], p)) + rcode = 1; +#else info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ } } } diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 3b41378..fd9146c 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -53,7 +53,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #if !defined(CONFIG_CPCI405) && !defined(CONFIG_AR405) && \ - !defined(CONFIG_PIP405) && \ + !defined(CONFIG_PIP405) && !defined(CONFIG_W7O) && \ !defined (CONFIG_WALNUT405) && !defined (CONFIG_ERIC) i2c_state_t state; @@ -71,7 +71,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) if (strncmp (argv[1], "res", 3) == 0) { printf ("I2C reset 50kHz ... "); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) i2c_init (); #else @@ -90,7 +90,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) else printf ("I2C reset %dkHz ... ", speed/1000); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) i2c_init (); #else @@ -118,7 +118,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) , i2c_addr, (ulong)data_addr, size); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -127,7 +127,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) rc = i2c_receive (i2c_addr, size, data_addr); @@ -145,7 +145,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -170,7 +170,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -178,7 +178,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) rc = i2c_send (i2c_addr, size, data_addr); @@ -193,7 +193,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -223,7 +223,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) i2c_addr, sec_addr, (ulong)data_addr, size); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -231,7 +231,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) rc = i2c_receive (i2c_addr, size, data_addr); @@ -248,7 +248,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -275,7 +275,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) i2c_addr, sec_addr, (ulong)data_addr, size); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else @@ -283,7 +283,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) rc = i2c_send (i2c_addr, size, data_addr); @@ -299,7 +299,7 @@ do_i2c (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ - defined(CONFIG_PIP405) || \ + defined(CONFIG_PIP405) || defined(CONFIG_W7O) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) #else diff --git a/common/command.c b/common/command.c index 2e210e5..ad14732 100644 --- a/common/command.c +++ b/common/command.c @@ -48,10 +48,12 @@ #include #include -#include /* board special functions */ -#include /* Floppy support */ +#include /* Floppy support */ #include #include +#include /* 4xx DCR register access */ + +#include /* board special functions */ #include @@ -193,92 +195,99 @@ cmd_tbl_t *find_cmd(const char *cmd) return NULL; /* not found */ } -cmd_tbl_t cmd_tbl[] = { - CMD_TBL_GO - CMD_TBL_RUN - - CMD_TBL_BOOTELF - CMD_TBL_BOOTVX +/* + * The commands in this table are sorted alphabetically by the + * command name and in descending order by the command name string + * length. This is to prevent conflicts in command name parsing. + * Please ensure that new commands are added according to that rule. + * Please use $(TOPDIR)/doc/README.commands as a reference AND make + * sure it gets updated. + */ +cmd_tbl_t cmd_tbl[] = { + CMD_TBL_ASKENV + CMD_TBL_ASM + CMD_TBL_AUTOSCRIPT + CMD_TBL_BASE + CMD_TBL_BDINFO + CMD_TBL_BOOTELF CMD_TBL_BOOTM CMD_TBL_BOOTP - CMD_TBL_TFTPB - CMD_TBL_RARPB - CMD_TBL_DHCP - CMD_TBL_DISK - CMD_TBL_SCSIBOOT - CMD_TBL_FDC + CMD_TBL_BOOTVX CMD_TBL_BOOTD - CMD_TBL_LOADS - CMD_TBL_LOADB - CMD_TBL_AUTOSCRIPT - CMD_TBL_MD - CMD_TBL_MM - CMD_TBL_NM - CMD_TBL_MW - CMD_TBL_CP + CMD_TBL_BREAK + CMD_TBL_BRGINFO + CMD_TBL_CARINFO CMD_TBL_CMP + CMD_TBL_CONINFO + CMD_TBL_CONTINUE + CMD_TBL_CP CMD_TBL_CRC - CMD_TBL_BASE - CMD_TBL_PRINTENV - CMD_TBL_SETENV - CMD_TBL_ASKENV - CMD_TBL_SAVEENV - CMD_TBL_PROTECT + CMD_TBL_DATE + CMD_TBL_DCACHE + CMD_TBL_DHCP + CMD_TBL_DISK + CMD_TBL_DMAINFO + CMD_TBL_DIS + CMD_TBL_ECHO + CMD_TBL_EEPROM + CMD_TBL_FCCINFO CMD_TBL_FLERASE + CMD_TBL_FDC CMD_TBL_FLINFO - CMD_TBL_BDINFO - CMD_TBL_IMINFO - CMD_TBL_REGINFO - CMD_TBL_PCIINFO - CMD_TBL_IRQINFO - CMD_TBL_CONINFO - CMD_TBL_IDE - CMD_TBL_SCSI - CMD_TBL_PINIT + CMD_TBL_GETDCR + CMD_TBL_GO + CMD_TBL_HELP + CMD_TBL_I2CINFO CMD_TBL_I2C - CMD_TBL_EEPROM - CMD_TBL_DATE - CMD_TBL_LOOP - CMD_TBL_MTEST CMD_TBL_ICACHE - CMD_TBL_DCACHE - CMD_TBL_RESET - CMD_TBL_KGDB - CMD_TBL_ECHO - CMD_TBL_SIUINFO - CMD_TBL_MEMCINFO - CMD_TBL_SITINFO #ifdef CONFIG_8260 CMD_TBL_ICINFO #endif - CMD_TBL_CARINFO + CMD_TBL_IDE + CMD_TBL_IMINFO CMD_TBL_IOPINFO - CMD_TBL_DMAINFO - CMD_TBL_FCCINFO - CMD_TBL_BRGINFO - CMD_TBL_I2CINFO + CMD_TBL_IRQINFO + CMD_TBL_KGDB + CMD_TBL_LOADB + CMD_TBL_LOADS + CMD_TBL_LOOP + CMD_TBL_MCCINFO + CMD_TBL_MD + CMD_TBL_MEMCINFO + CMD_TBL_MII + CMD_TBL_MM + CMD_TBL_MTEST + CMD_TBL_MUXINFO + CMD_TBL_MW + CMD_TBL_NEXT + CMD_TBL_NM + CMD_TBL_PCIINFO + CMD_TBL_PRINTENV + CMD_TBL_PROTECT + CMD_TBL_RARPB + CMD_TBL_RDUMP + CMD_TBL_PINIT + CMD_TBL_REGINFO + CMD_TBL_RESET + CMD_TBL_RUN + CMD_TBL_SAVEENV CMD_TBL_SCCINFO + CMD_TBL_SCSIBOOT + CMD_TBL_SCSI + CMD_TBL_SIINFO + CMD_TBL_SITINFO + CMD_TBL_SIUINFO + CMD_TBL_SETDCR + CMD_TBL_SETENV CMD_TBL_SMCINFO CMD_TBL_SPIINFO - CMD_TBL_MUXINFO - CMD_TBL_SIINFO - CMD_TBL_MCCINFO -#ifdef CMD_TBL_BSP /* Board Specific extensions ? */ - CMD_TBL_BSP -#endif + CMD_TBL_STACK + CMD_TBL_STEP + CMD_TBL_TFTPB CMD_TBL_VERS - CMD_TBL_HELP + CMD_TBL_BSP CMD_TBL_QUES - CMD_TBL_DIS - CMD_TBL_ASM - CMD_TBL_BREAK - CMD_TBL_STACK - CMD_TBL_CONTINUE - CMD_TBL_STEP - CMD_TBL_NEXT - CMD_TBL_RDUMP - CMD_TBL_MII /* the following entry terminates this table */ MK_CMD_TBL_ENTRY( NULL, 0, 0, 0, NULL, NULL, NULL ) }; diff --git a/common/flash.c b/common/flash.c index 6a197fb..6ff7305 100644 --- a/common/flash.c +++ b/common/flash.c @@ -22,8 +22,9 @@ */ #include +#include -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -64,10 +65,18 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */ if (from <= end && to >= info->start[i]) { if (flag & FLAG_PROTECT_CLEAR) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, info->start[i], 0); +#else info->protect[i] = 0; +#endif /* CFG_FLASH_PROTECTION */ } else if (flag & FLAG_PROTECT_SET) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, info->start[i], 1); +#else info->protect[i] = 1; +#endif /* CFG_FLASH_PROTECTION */ } } } diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 5b5ef09..add4aed 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o resetvec.o kgdb.o -OBJS = traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \ - 405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o 405_dimm.o +AOBJS = dcr.o +COBJS = traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \ + 405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o 405_dimm.o +OBJS = $(AOBJS) $(COBJS) all: .depend $(START) $(LIB) @@ -36,8 +38,8 @@ $(LIB): $(OBJS) ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ sinclude .depend diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S new file mode 100644 index 0000000..7102364 --- /dev/null +++ b/cpu/ppc4xx/dcr.S @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) + +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#define _ASMLANGUAGE + +/***************************************************************************** + * + * XXX - DANGER + * These routines make use of self modifying code. DO NOT CALL THEM + * UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not + * recommend them for use in anything other than an interactive + * debugging environment. This is mainly due to performance reasons. + * + ****************************************************************************/ + +/* + * static void _create_MFDCR(unsigned short dcrn) + * + * Builds a 'mfdcr' instruction for get_dcr + * function. + */ + .section ".text" + .align 2 + .type _create_MFDCR,@function +_create_MFDCR: + /* + * Build up a 'mfdcr' instruction formatted as follows: + * + * OPCD | RT | DCRF | XO | CR | + * ---------------|--------------|--------------|----| + * 0 5 | 6 10 | 11 20 | 21 30 | 31 | + * | | DCRN | | | + * 31 | %r3 | (5..9|0..4) | 323 | 0 | + * + * Where: + * OPCD = opcode - 31 + * RT = destination register - %r3 return register + * DCRF = DCRN # with upper and lower halves swapped + * XO = extended opcode - 323 + * CR = CR[CR0] NOT undefined - 0 + */ + rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ + rlwinm r3, r3, 5, 22, 26 + or r3, r3, r0 + slwi r3, r3, 10 + oris r3, r3, 0x3e30 /* RT = %r3 */ + ori r3, r3, 323 /* XO = 323 */ + slwi r3, r3, 1 /* CR = 0 */ + + mflr r4 + stw r3, 0(r4) /* Store instr in get_dcr() */ + dcbst r0, r4 /* Make sure val is written out */ + sync /* Wait for write to complete */ + icbi r0, r4 /* Make sure old instr is dumped */ + isync /* Wait for icbi to complete */ + + blr +.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR +/* end _create_MFDCR() */ + +/* + * static void _create_MTDCR(unsigned short dcrn, unsigned long value) + * + * Builds a 'mtdcr' instruction for set_dcr + * function. + */ + .section ".text" + .align 2 + .type _create_MTDCR,@function +_create_MTDCR: + /* + * Build up a 'mtdcr' instruction formatted as follows: + * + * OPCD | RS | DCRF | XO | CR | + * ---------------|--------------|--------------|----| + * 0 5 | 6 10 | 11 20 | 21 30 | 31 | + * | | DCRN | | | + * 31 | %r3 | (5..9|0..4) | 451 | 0 | + * + * Where: + * OPCD = opcode - 31 + * RS = source register - %r4 + * DCRF = dest. DCRN # with upper and lower halves swapped + * XO = extended opcode - 451 + * CR = CR[CR0] NOT undefined - 0 + */ + rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ + rlwinm r3, r3, 5, 22, 26 + or r3, r3, r0 + slwi r3, r3, 10 + oris r3, r3, 0x3e40 /* RS = %r4 */ + ori r3, r3, 451 /* XO = 451 */ + slwi r3, r3, 1 /* CR = 0 */ + + mflr r5 + stw r3, 0(r5) /* Store instr in set_dcr() */ + dcbst r0, r5 /* Make sure val is written out */ + sync /* Wait for write to complete */ + icbi r0, r5 /* Make sure old instr is dumped */ + isync /* Wait for icbi to complete */ + + blr +.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR +/* end _create_MTDCR() */ + + +/* + * unsigned long get_dcr(unsigned short dcrn) + * + * Return a given DCR's value. + */ + /* */ + /* XXX - This is self modifying code, hence */ + /* it is in the data section. */ + /* */ + .section ".data" + .align 2 + .globl get_dcr + .type get_dcr,@function +get_dcr: + mflr r0 /* Get link register */ + stwu r1, -32(r1) /* Save back chain and move SP */ + stw r0, +36(r1) /* Save link register */ + + bl _create_MFDCR /* Build following instruction */ + /* XXX - we build this instuction up on the fly. */ + .long 0 /* Get DCR's value */ + + lwz r0, +36(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +32 /* Remove frame from stack */ + blr /* Return to calling function */ +.Lfe3: .size get_dcr,.Lfe3-get_dcr +/* end get_dcr() */ + + +/* + * unsigned void set_dcr(unsigned short dcrn, unsigned long value) + * + * Return a given DCR's value. + */ + /* + * XXX - This is self modifying code, hence + * it is in the data section. + */ + .section ".data" + .align 2 + .globl set_dcr + .type set_dcr,@function +set_dcr: + mflr r0 /* Get link register */ + stwu r1, -32(r1) /* Save back chain and move SP */ + stw r0, +36(r1) /* Save link register */ + + bl _create_MTDCR /* Build following instruction */ + /* XXX - we build this instuction up on the fly. */ + .long 0 /* Set DCR's value */ + + lwz r0, +36(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +32 /* Remove frame from stack */ + blr /* Return to calling function */ +.Lfe4: .size set_dcr,.Lfe4-set_dcr +/* end set_dcr() */ +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/doc/README.commands b/doc/README.commands new file mode 100644 index 0000000..44552c7 --- /dev/null +++ b/doc/README.commands @@ -0,0 +1,91 @@ +# +# The commands in this table are sorted alphabetically by the +# command name and in descending order by the command name string +# length. This is to prevent conflicts in command name parsing. +# Please ensure that new commands are added according to that rule. +# See $(TOPDIR)/common/command.c +# +######################## +# +# command length +# +######################## +askenv 8 +as 2 +autoscr 5 +base 2 +bdinfo 2 +bootelf 7 +bootm 5 +bootp 5 +bootvx 6 +bootd 4 +break 2 +brginfo 3 +carinfo 3 +cmp 3 +coninfo 5 +continue 4 +cp 2 +crc32 3 +date 3 +dcache 2 +dhcp 4 +dmainfo 3 +ds 2 +echo 4 +eeprom 3 +erase 3 +fccinfo 3 +fdcboot 4 +flinfo 3 +getdcr 6 # IBM 4XX DCR registers +go 2 +help 1 +i2cinfo 4 +i2c 3 +icache 2 +icinfo 3 +ide 3 +iminfo 3 +iopinfo 3 +irqinfo 3 +kgdb 4 +loadb 5 +loads 5 +loop 4 +mccinfo 3 +md 2 +memcinfo 4 +mii 3 +mm 2 +mtest 5 +muxinfo 3 +mw 2 +next 4 +nm 2 +pciinfo 3 +pinit 4 +printenv 8 +protect 4 +rarpboot 4 +rdump 5 +reginfo 3 +reset 5 +run 3 +saveenv 4 +sccinfo 3 +scsiboot 5 +scsi 4 +siiinfo 3 +sitinfo 3 +siuinfo 3 +setdcr 6 # IBM 4XX DCR registers +setenv 6 +smcinfo 3 +spiinfo 3 +stack 5 +step 4 +tftpboot 4 +version 4 +? 1 diff --git a/include/cmd_bedbug.h b/include/cmd_bedbug.h index 705c022..ebe43f2 100644 --- a/include/cmd_bedbug.h +++ b/include/cmd_bedbug.h @@ -34,25 +34,25 @@ ), #define CMD_TBL_STEP MK_CMD_TBL_ENTRY( \ - "step", 1, 1, 1, do_bedbug_step, \ + "step", 4, 1, 1, do_bedbug_step, \ "step - single step execution.\n", \ " - single step execution.\n" \ ), #define CMD_TBL_NEXT MK_CMD_TBL_ENTRY( \ - "next", 1, 1, 1, do_bedbug_next, \ + "next", 4, 1, 1, do_bedbug_next, \ "next - single step execution, stepping over subroutines.\n",\ " - single step execution, stepping over subroutines.\n" \ ), #define CMD_TBL_STACK MK_CMD_TBL_ENTRY( \ - "where", 2, 1, 1, do_bedbug_stack, \ + "where", 5, 1, 1, do_bedbug_stack, \ "where - Print the running stack.\n", \ " - Print the running stack.\n" \ ), #define CMD_TBL_RDUMP MK_CMD_TBL_ENTRY( \ - "rdump", 2, 1, 1, do_bedbug_rdump, \ + "rdump", 5, 1, 1, do_bedbug_rdump, \ "rdump - Show registers.\n", \ " - Show registers.\n" \ ), diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 08cc40e..5d1411e 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -61,6 +61,7 @@ #define CFG_CMD_SCSI 0x08000000 /* SCSI Support */ #define CFG_CMD_AUTOSCRIPT 0x10000000 /* Autoscript Support */ #define CFG_CMD_MII 0x20000000 /* MII support */ +#define CFG_CMD_SETGETDCR 0x40000000 /* DCR support on 4xx */ #define CFG_CMD_BSP 0x80000000 /* Board Specific functions */ #define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */ diff --git a/include/cmd_dcr.h b/include/cmd_dcr.h new file mode 100644 index 0000000..373cf3f --- /dev/null +++ b/include/cmd_dcr.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * IBM 4XX DCR Functions + */ +#ifndef _CMD_DCR_H +#define _CMD_DCR_H + +#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) +#define CMD_TBL_GETDCR MK_CMD_TBL_ENTRY( \ + "getdcr", 6, 2, 1, do_getdcr, \ + "getdcr - Get an IBM PPC 4xx DCR's value\n", \ + "dcrn - return a DCR's value.\n" \ +), +#define CMD_TBL_SETDCR MK_CMD_TBL_ENTRY( \ + "setdcr", 6, 2, 1, do_setdcr, \ + "setdcr - Set an IBM PPC 4xx DCR's value\n", \ + "dcrn - set a DCR's value.\n" \ +), +extern int do_getdcr (cmd_tbl_t *, bd_t *, int, int, char *[]); +extern int do_setdcr (cmd_tbl_t *, bd_t *, int, int, char *[]); + +/* Supporting routines */ +extern unsigned long get_dcr(unsigned short dcrn); +extern unsigned long set_dcr(unsigned short dcrn, unsigned long value); + +#else + +#define CMD_TBL_GETDCR +#define CMD_TBL_SETDCR + +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ + +#endif /* _CMD_DCR_H */ diff --git a/include/cmd_immap.h b/include/cmd_immap.h index 6d811a3..26acd67 100644 --- a/include/cmd_immap.h +++ b/include/cmd_immap.h @@ -50,7 +50,7 @@ #ifdef CONFIG_8260 #define CMD_TBL_ICINFO MK_CMD_TBL_ENTRY( \ - "icinfo", 2, 1, 1, do_icinfo, \ + "icinfo", 3, 1, 1, do_icinfo, \ "icinfo - print Interrupt Controller registers\n", \ NULL \ ), diff --git a/include/cmd_rtc.h b/include/cmd_rtc.h index f956fc4..491ecd9 100644 --- a/include/cmd_rtc.h +++ b/include/cmd_rtc.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,12 +29,13 @@ #if (CONFIG_COMMANDS & CFG_CMD_DATE) -#define CMD_TBL_DATE MK_CMD_TBL_ENTRY( \ - "date", 3, 2, 1, do_date, \ - "date - get/set date & time\n", \ - "[MMDDhhmm[[CC]YY][.ss]]\n" \ +#define CMD_TBL_DATE MK_CMD_TBL_ENTRY( \ + "date", 3, 2, 1, do_date, \ + "date - get/set/reset date & time\n", \ + "[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n" \ " - without arguments: print date & time\n" \ - " - with argument: set the system date & time\n" \ + " - with numeric argument: set the system date & time\n" \ + " - with 'reset' argument: reset the RTC\n" \ ), int do_date (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); diff --git a/include/config_LANTEC.h b/include/config_LANTEC.h index 53ae99c..3dc93ea 100644 --- a/include/config_LANTEC.h +++ b/include/config_LANTEC.h @@ -84,6 +84,7 @@ #define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD) #define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) #define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ + & ~CFG_CMD_BSP \ & ~CFG_CMD_EEPROM \ & ~CFG_CMD_FDC \ & ~CFG_CMD_I2C \ diff --git a/include/config_MPC8260ADS.h b/include/config_MPC8260ADS.h index 80f9cfb..e08cdb5 100644 --- a/include/config_MPC8260ADS.h +++ b/include/config_MPC8260ADS.h @@ -85,6 +85,7 @@ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_BEDBUG | \ + CFG_CMD_BSP | \ CFG_CMD_DATE | \ CFG_CMD_EEPROM | \ CFG_CMD_FDC | \ diff --git a/include/config_TQM860L.h b/include/config_TQM860L.h index 595d450..2fc154a 100644 --- a/include/config_TQM860L.h +++ b/include/config_TQM860L.h @@ -90,7 +90,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#undef CFG_HUSH_PARSER /* use "hush" command parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/config_W7OLMC.h b/include/config_W7OLMC.h new file mode 100644 index 0000000..c49dd9b --- /dev/null +++ b/include/config_W7OLMC.h @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC405 family */ +#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ +#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootvx" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADADDR 0x10000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, 7200, \ + 9600, 19200, 14400, 28800, 33600, 38400, 57600, 76800, 115200, \ + 153600, 230400, 307200, 691200} + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* no pci plug-and-play */ +/* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ +#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ +#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +/*define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ +#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR + +#else /* Use Boot Flash for environment variables */ +/*----------------------------------------------------------------------- + * Flash EEPROM for environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (ATMEL 24C04N) + */ +#undef CONFIG_I2C_X /* 8 bit access */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ + +#define CONFIG_I2C + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above val. */ +#endif + +/* + * Init Memory Controller: + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ + + +/* On Chip Memory location */ +#define OCM_DATA_ADDR 0xF8000000 + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in RAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * FPGA(s) configuration + */ +#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ +#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ +#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ +#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ +#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ + +#endif /* __CONFIG_H */ + diff --git a/include/config_W7OLMG.h b/include/config_W7OLMG.h new file mode 100644 index 0000000..a876a0e --- /dev/null +++ b/include/config_W7OLMG.h @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC405 family */ +#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ +#define CONFIG_W7OLMG 1 /* ...specifically an LMG */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootvx" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADADDR 0x10000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper*/ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800, 7200, \ + 9600, 19200, 14400, 28800, 33600, 38400, 57600, 76800, 115200, \ + 153600, 230400, 307200, 691200} + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* no pci plug-and-play */ +/* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ +#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ +#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +/*define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ +#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR + +#else /* Use Boot Flash for environment variables */ +/*----------------------------------------------------------------------- + * Flash EEPROM for environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (ATMEL 24C04N) + */ +#undef CONFIG_I2C_X /* 8 bit access */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ + +#define CONFIG_I2C + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above val. */ +#endif + +/* + * Init Memory Controller: + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ + + +/* On Chip Memory location */ +#define OCM_DATA_ADDR 0xF8000000 + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * FPGA(s) configuration + */ +#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ +#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ +#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ +#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ +#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ + +#endif /* __CONFIG_H */ diff --git a/include/config_sbc8260.h b/include/config_sbc8260.h index ff205f2..f328b38 100644 --- a/include/config_sbc8260.h +++ b/include/config_sbc8260.h @@ -292,8 +292,7 @@ CFG_CMD_I2C | \ CFG_CMD_REGINFO | \ CFG_CMD_IMMAP | \ - CFG_CMD_MII | \ - CFG_CMD_BSP) + CFG_CMD_MII) /* Where do the internal registers live? */ diff --git a/include/flash.h b/include/flash.h index 65b332f..831385f 100644 --- a/include/flash.h +++ b/include/flash.h @@ -21,6 +21,8 @@ * MA 02111-1307 USA */ +#ifndef _FLASH_H_ +#define _FLASH_H_ /*----------------------------------------------------------------------- * FLASH Info: contains chip specific data, per FLASH bank @@ -36,17 +38,22 @@ typedef struct { /* Prototypes */ -unsigned long flash_init (void); -void flash_print_info (flash_info_t *); -int flash_erase (flash_info_t *, int, int); -int flash_sect_erase (ulong addr_first, ulong addr_last); -int flash_sect_protect (int flag, ulong addr_first, ulong addr_last); +extern unsigned long flash_init (void); +extern void flash_print_info (flash_info_t *); +extern int flash_erase (flash_info_t *, int, int); +extern int flash_sect_erase (ulong addr_first, ulong addr_last); +extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last); /* common/flash.c */ -void flash_protect (int flag, ulong from, ulong to, flash_info_t *info); -int flash_write (uchar *, ulong, ulong); -flash_info_t *addr2info (ulong); -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); +extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info); +extern int flash_write (uchar *, ulong, ulong); +extern flash_info_t *addr2info (ulong); +extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); + +/* board/?/flash.c */ +#if defined(CFG_FLASH_PROTECTION) +extern int flash_real_protect(flash_info_t *info, long sector, int prot); +#endif /* CFG_FLASH_PROTECTION */ /*----------------------------------------------------------------------- * return codes from flash_write(): @@ -251,3 +258,4 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ #define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ +#endif /* _FLASH_H_ */ diff --git a/include/i2c.h b/include/i2c.h index 0c4875f..e4e6ddd 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -14,7 +14,7 @@ int i2c_write (uchar *addr, int alen, uchar *buffer, int len); #if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \ defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || \ - defined (CONFIG_PIP405) + defined (CONFIG_PIP405) || defined (CONFIG_W7O) void i2c_init(void); int i2c_receive(unsigned char address, diff --git a/include/ppcboot.h b/include/ppcboot.h index fa86d43..e971f2f 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -200,7 +200,8 @@ void inline setenv (char *, char *); defined (CONFIG_OCRTC) || \ defined (CONFIG_DASA_SIM) || \ defined (CONFIG_ERIC) || \ - defined (CONFIG_MOUSSE) + defined (CONFIG_MOUSSE) || \ + defined (CONFIG_W7O) /* $(CPU)/405gp_pci.c */ void pci_init (bd_t *); void pciinfo (int); @@ -209,11 +210,12 @@ void pciinfo (int); #if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \ defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \ defined(CONFIG_CPCI405) || defined(CONFIG_PCU_E) || \ + defined(CONFIG_EVB64260) || defined(CONFIG_LWMON) || \ defined(CONFIG_EVB64260) || defined(CONFIG_LWMON) || \ - defined(CONFIG_CCM) || \ + defined(CONFIG_CCM) || defined(CONFIG_W7O) || \ defined(CONFIG_MISC_INIT_R) /* cogent - $(BOARD)/mb.c */ -/* SXNI855T and HYMOD - $(BOARD)/$(BOARD).c */ +/* SXNI855T, HYMOD, and W7O - $(BOARD)/$(BOARD).c */ # if !defined(CONFIG_PCU_E) && !defined(CONFIG_CCM) int misc_init_f (void); # endif @@ -305,6 +307,7 @@ void load_sernum_ethaddr(bd_t *bd); defined(CONFIG_RPXSUPER) || \ defined(CONFIG_CU824) || \ defined(CONFIG_EVB64260) || \ + defined(CONFIG_W7O) || \ defined(CONFIG_BOARD_PRE_INIT) /* $(BOARD)/$(BOARD).c */ int board_pre_init (void); diff --git a/ppc/ticks.S b/ppc/ticks.S index 79c3f24..a854722 100644 --- a/ppc/ticks.S +++ b/ppc/ticks.S @@ -1,5 +1,7 @@ /* * (C) Copyright 2000 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * base on code by * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -43,18 +45,18 @@ get_ticks: */ .globl wait_ticks wait_ticks: -1: mftbu r4 - mftb r5 - mftbu r6 - cmp 0,r4,r6 - bne 1b /* Get [synced] base time */ - addc r9,r5,r3 /* Compute end time */ - addze r8,r4 -2: mftbu r4 - cmp 0,r4,r8 - blt 2b - bgt 3f - mftb r5 - cmp 0,r5,r9 - blt 2b -3: blr + mflr r8 /* save link register */ + mr r7, r3 /* save tick count */ + bl get_ticks /* Get start time */ + + /* Calculate end time */ + addc r7, r4, r7 /* Compute end time lower */ + addze r6, r3 /* and end time upper */ + +1: bl get_ticks /* Get current time */ + subfc r4, r4, r7 /* Subtract current time from end time */ + subfe. r3, r3, r6 + bge 1b /* Loop until time expired */ + + mtlr r8 /* restore link register */ + blr diff --git a/ppc/time.c b/ppc/time.c index 128fee4..eee8936 100644 --- a/ppc/time.c +++ b/ppc/time.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -26,9 +26,20 @@ /* ------------------------------------------------------------------------- */ +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ unsigned long usec2ticks(unsigned long usec) { - ulong ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + ulong ticks; + + if (usec < 1000) { + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + } else { + ticks = ((usec / 10) * (get_tbclk() / 100000)); + } return (ticks); } diff --git a/rtc/Makefile b/rtc/Makefile index 107cf32..45b25aa 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = librtc.a -OBJS = date.o pcf8563.o mpc8xx.o mc146818.o ds174x.o +OBJS = date.o pcf8563.o mpc8xx.o mc146818.o ds174x.o m48t35ax.o all: $(LIB) diff --git a/rtc/m48t35ax.c b/rtc/m48t35ax.c new file mode 100644 index 0000000..9fd9041 --- /dev/null +++ b/rtc/m48t35ax.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for ST Electronics M48T35Ax RTC + */ + +/*#define DEBUG */ + + +#include +#include +#include +#include +#include "error.h" + +#if defined(CONFIG_RTC_M48T35A) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, cent_day, date, month, year; + uchar ccr; /* Clock control register */ + + /* Lock RTC for read using clock control register */ + ccr = rtc_read(0); + ccr = ccr | 0x40; + rtc_write(0, ccr); + + sec = rtc_read (0x1); + min = rtc_read (0x2); + hour = rtc_read (0x3); + cent_day= rtc_read (0x4); + date = rtc_read (0x5); + month = rtc_read (0x6); + year = rtc_read (0x7); + + /* UNLock RTC */ + ccr = rtc_read(0); + ccr = ccr & 0xBF; + rtc_write(0, ccr); + + debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, month, date, cent_day, + hour, min, sec ); + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (date & 0x3F); + tmp->tm_mon = bcd2bin (month & 0x1F); + tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900); + tmp->tm_wday = bcd2bin (cent_day & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar ccr; /* Clock control register */ + uchar century; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* Lock RTC for write using clock control register */ + ccr = rtc_read(0); + ccr = ccr | 0x80; + rtc_write(0, ccr); + + rtc_write (0x07, bin2bcd(tmp->tm_year % 100)); + rtc_write (0x06, bin2bcd(tmp->tm_mon)); + rtc_write (0x05, bin2bcd(tmp->tm_mday)); + + century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20; + rtc_write (0x04, bin2bcd(tmp->tm_wday) | century); + + rtc_write (0x03, bin2bcd(tmp->tm_hour)); + rtc_write (0x02, bin2bcd(tmp->tm_min )); + rtc_write (0x01, bin2bcd(tmp->tm_sec )); + + /* UNLock RTC */ + ccr = rtc_read(0); + ccr = ccr & 0x7F; + rtc_write(0, ccr); +} + +void rtc_reset (void) +{ + uchar val; + + /* Clear all clock control registers */ + rtc_write (0x0, 0x80); /* No Read Lock or calibration */ + + /* Clear stop bit */ + val = rtc_read (0x1); + val &= 0x7f; + rtc_write(0x1, val); + + /* Enable century / disable frequency test */ + val = rtc_read (0x4); + val = (val & 0xBF) | 0x20; + rtc_write(0x4, val); + + /* Clear write lock */ + rtc_write(0x0, 0); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read (uchar reg) +{ + uchar val; + val = *(unsigned char *) + ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg); + return val; +} + +static void rtc_write (uchar reg, uchar val) +{ + *(unsigned char *) + ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg) = val; +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#if 0 +int rtctest(void){ + struct rtc_time *tmp; + uchar tchar; + + log_stat(ERR_RTCG); + *(unsigned char *)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9) = 0xaa; + tchar = *(unsigned char *)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9); + tchar = tchar ^ 0xaa; + if( tchar != 0xaa ) log_warn(ERR_RTCBAT); + rtc_get(tmp); + if((tmp->tm_sec > 59) | + (tmp->tm_min > 59) | + (tmp->tm_hour > 23) | + (tmp->tm_mday < 1 ) | (tmp->tm_mday > 31) | + (tmp->tm_mon < 1 ) | (tmp->tm_mon > 12) | + (tmp->tm_year > 99) | + (tmp->tm_wday < 1 ) | (tmp->tm_wday > 7 ) | + (tmp->tm_wday < 1 ) | (tmp->tm_wday > 7 ) ) + { + log_warn(ERR_RTCVAL); + rtc_reset(); + return 0; + } + return 1; +} +#endif + +#endif /* CONFIG_RTC_M48T35A && CFG_CMD_DATE */ diff --git a/tools/Makefile b/tools/Makefile index 3fdda0d..d36ee35 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -48,8 +48,8 @@ endif # # Use native tools and options # -CPPFLAGS = -Wall -pedantic -I../include -I.. -DTEXT_BASE=$(TEXT_BASE) -CFLAGS = $(CPPFLAGS) -O +CPPFLAGS = -I../include -I.. -DTEXT_BASE=$(TEXT_BASE) +CFLAGS = -Wall -pedantic $(CPPFLAGS) -O AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) CC = $(HOSTCC) MAKEDEPEND = makedepend diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index 4ef25fb..e891f9d 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -30,8 +30,8 @@ OBJS = gdbsend.o gdbcont.o astest.o error.o remote.o serial.o # # Use native tools and options # -CPPFLAGS = -Wall -pedantic -O -I$(BFD_ROOT_DIR)/include -CFLAGS = $(CPPFLAGS) +CPPFLAGS = -I$(BFD_ROOT_DIR)/include +CFLAGS = -Wall -pedantic -O $(CPPFLAGS) CC = $(HOSTCC) MAKEDEPEND = makedepend diff --git a/tools/mkimage.c b/tools/mkimage.c index 315aaaf..5c186b5 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -18,7 +18,7 @@ #include #include -#if defined(__BEOS__) || defined(__NetBSD__) +#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) #include #endif @@ -44,7 +44,7 @@ typedef unsigned int uint32_t; extern int errno; #ifndef MAP_FAILED -#define MAP_FAILED -1 +#define MAP_FAILED (-1) #endif char *cmdname; @@ -419,7 +419,7 @@ NXTARG: ; ptr = (unsigned char *)mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); - if (ptr == MAP_FAILED) { + if (ptr == (unsigned char *)MAP_FAILED) { fprintf (stderr, "%s: Can't map %s: %s\n", cmdname, imagefile, strerror(errno)); exit (EXIT_FAILURE); @@ -490,7 +490,7 @@ copy_file (int ifd, const char *datafile, int pad) ptr = (unsigned char *)mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); - if (ptr == MAP_FAILED) { + if (ptr == (unsigned char *)MAP_FAILED) { fprintf (stderr, "%s: Can't read %s: %s\n", cmdname, datafile, strerror(errno)); exit (EXIT_FAILURE);