From: wdenk Date: Mon, 8 Oct 2001 16:49:00 +0000 (+0000) Subject: * Patch by David Updegraff, 05 Oct 2001: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=7317c39ca820ab6e18a06fa179607a2d498f3251;p=users%2Frw%2Fppcboot.git * Patch by David Updegraff, 05 Oct 2001: - Added "reginfo" command for 405GP - Added DHCP vendor extensions - Added configuration for Cray L1 board --- diff --git a/CHANGELOG b/CHANGELOG index bd1b5f2..414ebaa 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,11 @@ To do: Modifications for 1.0.6: ====================================================================== +* Patch by David Updegraff, 05 Oct 2001: +- Added "reginfo" command for 405GP +- Added DHCP vendor extensions +- Added configuration for Cray L1 board + * Patch by Jon Diekema, 17 Sep 2001: - Make "mtest" command more verbose - SBC8260 board can support either a 16 MB or a 64 MB DIMM diff --git a/CREDITS b/CREDITS index e451f8a..9f4e011 100644 --- a/CREDITS +++ b/CREDITS @@ -147,6 +147,10 @@ N: Erik Theisen E: etheisen@mindspring.com D: MBX8xx patches +N: David Updegraff +E: dave@cray.com +D: Port to Cray L1 board; DHCP vendor extensions + N: Christian Vejlbo E: christian.vejlbo@tellabs.com D: FADS860T ethernet support diff --git a/MAKEALL b/MAKEALL index cb5a91d..469a94b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -32,9 +32,10 @@ LIST="$LIST \ LIST="$LIST \ ADCIOP AR405 \ CANBT CPCI405 \ - CPCIISER4 DASA_SIM \ - ERIC OCRTC \ - PIP405 WALNUT405 \ + CPCIISER4 CRAYL1 \ + DASA_SIM ERIC \ + OCRTC PIP405 \ + WALNUT405 \ " ######################################################################### diff --git a/Makefile b/Makefile index cc076b4..ef27856 100644 --- a/Makefile +++ b/Makefile @@ -389,13 +389,13 @@ CPCIISER4_config: unconfig echo "VENDOR = esd" >>config.mk ; \ echo "#include " >config.h -OCRTC_config: unconfig - @echo "Configuring for $(@:_config=) Board..." ; \ +CRAYL1_config:unconfig + @echo "Configuring for $(@:_config=) Board..(SV2 L1)." ; \ cd include ; \ echo "ARCH = ppc" > config.mk ; \ - echo "BOARD = ocrtc">>config.mk ; \ + echo "BOARD = L1" >>config.mk ; \ echo "CPU = ppc4xx" >>config.mk ; \ - echo "VENDOR = esd" >>config.mk ; \ + echo "VENDOR = cray" >>config.mk ; \ echo "#include " >config.h DASA_SIM_config: unconfig @@ -415,6 +415,15 @@ ERIC_config:unconfig echo "CPU = ppc4xx" >>config.mk ; \ echo "#include " >config.h +OCRTC_config: unconfig + @echo "Configuring for $(@:_config=) Board..." ; \ + cd include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = ocrtc">>config.mk ; \ + echo "CPU = ppc4xx" >>config.mk ; \ + echo "VENDOR = esd" >>config.mk ; \ + echo "#include " >config.h + PIP405_config:unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c new file mode 100644 index 0000000..2f71af0 --- /dev/null +++ b/board/cray/L1/L1.c @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "L1.h" +#include +#include <405gp_i2c.h> +#include +#include +#include +#include +#include + +#define FACTORY_SETTINGS 0xFFFC0000 + +#define DHCP_BOOTFILE 67 +#define DHCP_ROOTPATH 17 +#define DHCP_L1_FIRMWARE 220 +#define DHCP_L1_KERNEL 221 +#define DHCP_L1_ROOTFS 222 + +#define XTFTP 0x100000 /* TFTP things to this addr for staging */ +#define TFTP_NAMELEN 128 + +/* Things DHCP server can tellme about. If there's no flash address, then + * they dont participate in 'update' to flash, and we force their values + * back to '0' every boot to be sure to get them fresh from DHCP + */ +typedef struct dhcp_item_s { + u8 dhcp_option; + char tftpname[TFTP_NAMELEN]; + char envname[16]; + u32 new_version; + u32 flashaddr; + u32 flashlen; +} dhcp_item_t; +static dhcp_item_t Things[] = { + {DHCP_BOOTFILE, "", "bootfile", 0, 0, 0}, + {DHCP_ROOTPATH, "", "rootpath", 0, 0, 0}, + {DHCP_L1_FIRMWARE, "", "L1-firmware", 0, 0xFFFE0000, 0x020000}, + {DHCP_L1_KERNEL, "", "L1-kernel", 0, 0xFFF00000, 0x0C0000}, + {DHCP_L1_ROOTFS, "", "L1-rootfs", 0, 0xFFC00000, 0x300000} +}; +#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) +static char buf[128]; + +extern flash_info_t flash_info[]; /* info for FLASH chips */ +extern char BootFile[]; /* TFTP filename in net/net.c */ +extern ulong NetBootFileXferSize; + +int board_pre_init (void) +{ + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical*/ + mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + + +int checkboard (void) +{ +#if 0 + unsigned char *s = getenv("serial#"); + unsigned char *e; + + if (!s || strncmp(s, "CRAY_L1", 7)) + { + printf ("### No HW ID - assuming CRAY_L1\n"); + } + else + { + for (e=s; *e; ++e) { + if (*e == ' ') + break; + } + + for ( ; sih_time; + to_tm (timestamp, &tm); + printf ( +"Welcome to PPCBOOT on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); + + if ((s = getenv("ethaddr")) == NULL) + { + printf ("No ENVIRONMENT:"); + e = (unsigned char *)(FACTORY_SETTINGS); + if (*e != '0') + { + printf ("No valid MAC address in flash location 0x3C0000!\n"); + } + else + { + printf ("Factory MAC: %s\n",e); + setenv ("ethaddr", e); + // Serial# will later be sucked out of i2c + // setenv ("serial#", "CRAY_L1"); + setenv ("dhcp_client_id", "crayL1"); + needsave++; + } + } +// Also establish the baseline values for firmware,kernel,rootfs + for ( thing=0; thing < N_THINGS; thing++) + { +// If the env setting doesn't yet exist, or for things that are NOT associated +// with save-regions in firmware (i.e. only believe fresh DHCP values) we +// set zero baselines. + if (!Things[thing].flashaddr || (getenv(Things[thing].envname) == NULL)) + { + setenv (Things[thing].envname,""); + needsave++; + } + } + + return; +} + +/* + * ..in process... + */ +/* ------------------------------------------------------------------------- */ + + +void do_crayL1(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ +unsigned long addr, valu,old; +u8 thing,need_save=0,only, *ptr; + + + if (strcmp(argv[1], "update") == 0) // TFTP down updates. + { + only = 0xff; + if ( argc > 2 ) + { + for ( thing=0; thing < N_THINGS; thing++) + { + if (strcmp(argv[2], Things[thing].envname) == 0) + { + only = thing; + break; + } + } + if ( only == 0xff ) + { + printf ("update one of: [ "); + for ( thing=0; thing < N_THINGS; thing++) + printf ("%s ",Things[thing].envname); + printf ("]\n"); + return; + } + else + printf ("Update %s\n",Things[only].envname); + } + + for ( thing=0; thing < N_THINGS; thing++) + { + if (((only != 0xff) && (thing != only)) || !Things[thing].flashaddr) + continue; + printf ("check Update: %s..",Things[thing].envname); + if ( strlen (Things[thing].tftpname)) + { + old = simple_strtoul(getenv(Things[thing].envname),NULL,10); + if ( Things[thing].new_version <= old ) + { + printf ("..already up to date\n"); + continue; + } + printf ("needs updating, will TFTP <%s>\n", + Things[thing].tftpname); + + load_addr = XTFTP; + strcpy (BootFile,Things[thing].tftpname); + if (NetLoop(bd, TFTP) == 0) + printf ("fail to TFTP %s\n",Things[thing].tftpname); + else + { + valu = NetBootFileXferSize & 0xffff0000; + if (NetBootFileXferSize & 0xffff) + valu += 0x10000; + + printf ("erasing flash regions: %x thru %lx\n", + Things[thing].flashaddr, + Things[thing].flashaddr + valu - 1); + + flash_sect_erase( Things[thing].flashaddr, + Things[thing].flashaddr + valu - 1); + printf ("updating flash: %lx bytes from %x to %x\n", + valu, XTFTP, Things[thing].flashaddr); + flash_write ((uchar *)XTFTP, Things[thing].flashaddr, valu); + + printf ("Updating environmet setting..\n"); + memset (Things[thing].tftpname,0,TFTP_NAMELEN); + sprintf( buf,"%d",Things[thing].new_version); + setenv (Things[thing].envname,buf); + need_save = 1; + } + } + else + printf ("No TFTP update file DHCP-provided for %s\n", + Things[thing].envname); + } + if (need_save) + do_saveenv (NULL,NULL,0,0,NULL); + return; + } + + if (strcmp(argv[1], "boot") == 0) // boot ourselves up. + { +// Some process has happened; probably DHCP, and things have been updated. +// I normally want to boot from image in flash, using rootfs in flash; that +// is the contents of the 'ramboot' environment variable. If server has +// given me a bootfile and rootpath, then we will assume that we are to boot +// that way, with the 'nfsboot' environment string. Regardless, we ALWAYS +// set up the ip= boot argument, since kernel lacks DHCP support still. + + if ((ptr = getenv ("bootfile")) && strlen(ptr)) + { + load_addr = XTFTP; + strcpy (BootFile,ptr); + if (NetLoop(bd, TFTP) == 0) + printf ("fail to TFTP boot image <%s>; revert to flash.\n",ptr); + } + else + load_addr = 0xfff00000; /* flash kernel address */ + + if ((ptr = getenv ("rootpath")) && strlen(ptr)) + run_command ("setenv bootargs " + "root=/dev/nfs nfsroot=$(serverip):$(rootpath) " + " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off" + " ro devfs=mount",bd,0); + else + run_command ("setenv bootargs " + "root=/dev/mtdblock/0 " + " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off" + " ro devfs=mount",bd,0); + + addr = load_addr; + do_bootm (cmdtp, bd, 0, 1, NULL); + return; + } + if (strcmp(argv[1], "regs") == 0) // Dump DCRs + { + printf("cray regs command..UNIMPLEMENTED.\n"); + return; + } + if (strcmp(argv[1], "mfdcr") == 0) // read a DCR from argv[2] (HEX!) + { + addr = simple_strtoul(argv[2], NULL, 16); + printf("cray mfcdr command: read from DCR 0x%lx UNIMPLEMENTED.\n",addr); + return; + } + if (strcmp(argv[1], "mtdcr") == 0) // write a DCR from argv[2] (HEX!) + { + addr = simple_strtoul(argv[2], NULL, 16); + valu = simple_strtoul(argv[3], NULL, 16); + printf("cray mtcdr command: write 0x%lx to DCR 0x%lx UNIMPLEMENTED\n", + valu, addr); + return; + } + + printf("Usage:\n%s\n", cmdtp->usage); + return; +} + + + +/* ------------------------------------------------------------------------- */ + +/* ------------------------------------------------------------------------- */ +/* + initdram(int board_type) does NOT! read the EEPROM on IIc, but instead + returns hardwire 32M. +*/ +/* ------------------------------------------------------------------------- */ +long int initdram (int board_type) +{ + return (32*1024*1024); +} + +/* ------------------------------------------------------------------------- */ +/* stubs so we can print dates w/o any nvram RTC.*/ +void rtc_get (struct rtc_time *tmp) {return;} +void rtc_set (struct rtc_time *tmp) {return;} +void rtc_reset (void) {return;} + + +/* ------------------------------------------------------------------------- */ + +u8 *dhcp_vendorex_prep(u8 *e) +{ +u8 thing; +char *ptr; + +/* my DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv("dhcp_client_id"))) + { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + *e++ = 55; /* Parameter Request List */ + *e++ = N_THINGS; + for ( thing=0; thing < N_THINGS; thing++) + *e++ = Things[thing].dhcp_option; + *e++ = 255; + + return e; +} + +/* ------------------------------------------------------------------------- */ +u8 *dhcp_vendorex_proc(u8 *popt) +{ +u8 oplen,thing,i; + +/* have TFTP filenames and some version#. If no version# then version=0. */ + oplen = *(popt + 1); + + for ( thing=0; thing < N_THINGS; thing++) + { + if (*popt == Things[thing].dhcp_option) + { + for(i=0;((i have#=%s need#=%d\n", + Things[thing].envname, + Things[thing].tftpname, + getenv (Things[thing].envname), + Things[thing].new_version); + break; + } + } + return ( thing >= N_THINGS ? NULL : popt); +} diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h new file mode 100644 index 0000000..c16b28b --- /dev/null +++ b/board/cray/L1/L1.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip + * + * Start Address Length + * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- + * | Failsafe Linux Image | (1M) + * +=======================+ 0xFFD0_0000 + * | (Reserved FlashFiles) | (1M) + * +=======================+ 0xFFE0_0000 + * | Failsafe RootFS | (1M) + * +=======================+ 0xFFF0_0000 + * | | + * | U N U S E D | + * | | + * +-----------------------+ 0xFFFD_0000 PPCBOOT image header (64 bytes) + * | environment settings | (64k) + * +-----------------------+ 0xFFFE_0000 PPCBOOT image header (64 bytes) + * | PPCBOOT | 0xFFFE_0040 _start of ppcboot + * | | 0xFFFE_FFFC reset vector - branch to _start + * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- + *****************************************************************************/ diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile new file mode 100644 index 0000000..f695ad0 --- /dev/null +++ b/board/cray/L1/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cray/L1/config.mk b/board/cray/L1/config.mk new file mode 100644 index 0000000..a80a14c --- /dev/null +++ b/board/cray/L1/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +#TEXT_BASE = 0xFFF80000 +# Note: I make an "image" from ppcboot itself, which prefixes 0x40 bytes of +# header info, hence start address is thus shifted. +TEXT_BASE = 0xFFFE0040 diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c new file mode 100644 index 0000000..9f00961 --- /dev/null +++ b/board/cray/L1/flash.c @@ -0,0 +1,470 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +/* + * Modified July 20, 2001 + * Strip down to support ONLY the AMD29F032B. + * Dave Updegraff - Cray, Inc. dave@cray.com + */ + +#include +#include +#include + +/* The flash chip we use... */ +#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ +#define FLASH_AM320B 0x0009 + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; isector_count; i++) + info->start[i] = base + (i * 0x00010000); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_F032B: + info->flash_id += FLASH_AM320B; + info->sector_count = 64; + info->size = 0x0400000; /* => 4 MB */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +void flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); // CLH + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S new file mode 100644 index 0000000..98d352d --- /dev/null +++ b/board/cray/L1/init.S @@ -0,0 +1,247 @@ +//------------------------------------------------------------------------------+ +// +// This source code has been made available to you by IBM on an AS-IS +// basis. Anyone receiving this source is licensed under IBM +// copyrights to use it in any way he or she deems fit, including +// copying it, modifying it, compiling it, and redistributing it either +// with or without modifications. No license under IBM patents or +// patent applications is to be implied by the copyright license. +// +// Any user of this software should understand that IBM cannot provide +// technical support for this software and will not be responsible for +// any consequences resulting from the use of this software. +// +// Any person who transfers this source code or any derivative work +// must include the IBM copyright notice, this paragraph, and the +// preceding two paragraphs in the transferred software. +// +// COPYRIGHT I B M CORPORATION 1995 +// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +//------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Function: ext_bus_cntlr_init +// Description: Initializes the External Bus Controller for the external +// peripherals. IMPORTANT: For pass1 this code must run from +// cache since you can not reliably change a peripheral banks +// timing register (pbxap) while running code from that bank. +// For ex., since we are running from ROM on bank 0, we can NOT +// execute the code that modifies bank 0 timings from ROM, so +// we run it from cache. +// Bank 0 - Flash and SRAM +// Bank 1 - NVRAM/RTC +// Bank 2 - Keyboard/Mouse controller +// Bank 3 - IR controller +// Bank 4 - not used +// Bank 5 - not used +// Bank 6 - not used +// Bank 7 - FPGA registers +//-----------------------------------------------------------------------------#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ +#define FPGA_BRDC 0xF0300004 + +#include +#include + +#include +#include + +// CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty +// except for #1 which we use for DMA'ing to IOCA-like things, so the +// control registers to set that up are determined by what we've +// empirically discovered work there. + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 // save link register + bl ..getAddr +..getAddr: + mflr r3 // get address of ..getAddr + mtlr r4 // restore link register + addi r4,0,14 // set ctr to 10; used to prefetch + mtctr r4 // 10 cache lines to fit this function + // in cache (gives us 8x10=80 instrctns) +..ebcloop: + icbt r0,r3 // prefetch cache line for addr in r3 + addi r3,r3,32 // move to next cache line + bdnz ..ebcloop // continue for 10 cache lines + + //------------------------------------------------------------------- + // Delay to ensure all accesses to ROM are complete before changing + // bank 0 timings. 200usec should be enough. + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp: + bdnz ..spinlp // spin loop + + + //---------------------------------------------------------------------- + // Memory Bank 0 (Flash and SRAM) initialization + //---------------------------------------------------------------------- + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x9B01 + ori r4,r4,0x5480 + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0( 8 bits) + mtdcr ebccfgd,r4 + + //---------------------------------------------------------------------- + // Memory Bank 1 (NVRAM/RTC) initialization + // CRAY:the L1 has NOT this bank; it is tied to SV2/IOCA/etc/ instead + // and we do DMA on it. The ConfigurationRegister part is threfore + // almost arbitrary, except that our linux driver needs to know the + // address, but it can query, it.. + // + // The AccessParameter is CRITICAL, + // thouch, since it needs to agree with the electrical timings on the + // IOCA parallel interface. That value is: 0x0185,4380 + // BurstModeEnable BME=0 + // TransferWait TWT=3 + // ChipSelectOnTiming CSN=1 + // OutputEnableOnTimimg OEN=1 + // WriteByteEnableOnTiming WBN=1 + // WriteByteEnableOffTiming WBF=0 + // TransferHold TH=1 + // ReadyEnable RE=1 + // SampleOnReady SOR=1 + // ByteEnableMode BEM=0 + // ParityEnable PEN=0 + // all reserved bits=0 + //---------------------------------------------------------------------- + //---------------------------------------------------------------------- + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,0x0185 // hiword + ori r4,r4,0x4380 // loword + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), + ori r4,r4,0x8000 // BW=0x0( 8 bits) + mtdcr ebccfgd,r4 + + blr + +//----------------------------------------------------------------------------- +// Function: sdram_init +// Description: Configures SDRAM memory banks. +// Auto Memory Configuration option reads the SDRAM EEPROM +// via the IIC bus and then configures the SDRAM memory +// banks appropriately. If Auto Memory Configuration is +// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is +// plugged, ie. the DIMM that shipped wih the Eval board. +//----------------------------------------------------------------------------- + .globl sdram_init + +sdram_init: + + mflr r31 + +//------------------------------------------------------------------- +// Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) +//------------------------------------------------------------------- + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,0x0006 + ori r4,r4,0x2001 + mtdcr memcfgd,r4 + +//------------------------------------------------------------------- +// Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. +// To set the appropriate timings, we need to know the SDRAM speed. +// We can use the PLB speed since the SDRAM speed is the same as +// the PLB speed. The PLB speed is the FBK divider times the +// 405GP reference clock, which on the Walnut board is 33Mhz. +// Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is +// 100Mhz; if FBK is 3, SDRAM is 133Mhz. +// NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and +// maybe 133Mhz. +//------------------------------------------------------------------- + mfdcr r5,strap // determine FBK divider + // via STRAP reg to calc PLB speed. + // SDRAM speed is the same as the PLB + // speed. + rlwinm r4,r5,4,0x3 // get FBK divide bits + +..chk_66: + cmpi %cr0,0,r4,0x1 + bne ..chk_100 + addis r6,0,0x0085 // SDTR1 value for 66Mhz + ori r6,r6,0x4005 + addis r7,0,0x03F8 // RTR value for 66Mhz + b ..sdram_ok +..chk_100: + cmpi %cr0,0,r4,0x2 + bne ..chk_133 + addis r6,0,0x0086 // SDTR1 value for 100Mhz + ori r6,r6,0x400D + addis r7,0,0x05F0 // RTR value for 100Mhz + b ..sdram_ok +..chk_133: + addis r6,0,0x0107 // SDTR1 value for 133Mhz + ori r6,r6,0x4015 + addis r7,0,0x07F0 // RTR value for 133Mhz + +..sdram_ok: + //------------------------------------------------------------------- + // Set SDTR1 + //------------------------------------------------------------------- + addi r4,0,mem_sdtr1 + mtdcr memcfga,r4 + mtdcr memcfgd,r6 + + //------------------------------------------------------------------- + // Set RTR + //------------------------------------------------------------------- + addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + //------------------------------------------------------------------- + // Delay to ensure 200usec have elapsed since reset. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + //------------------------------------------------------------------- + addis r3,0,0x0000 + ori r3,r3,0xA000 // ensure 200usec have passed since reset + mtctr r3 +..spinlp2: + bdnz ..spinlp2 // spin loop + + //------------------------------------------------------------------- + // Set memory controller options reg, MCOPT1. + // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + // read/prefetch. + //------------------------------------------------------------------- + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 // set DC_EN=1 + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + //------------------------------------------------------------------- + // Delay to ensure 10msec have elapsed since reset. This is + // required for the MPC952 to stabalize. Assume worst + // case that the core is running 200Mhz: + // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles + // This delay should occur before accessing SDRAM. + //------------------------------------------------------------------- + addis r3,0,0x001E + ori r3,r3,0x8480 // ensure 10msec have passed since reset + mtctr r3 +..spinlp3: + bdnz ..spinlp3 // spin loop + + mtlr r31 // restore lr + blr diff --git a/board/cray/L1/ppcboot.lds b/board/cray/L1/ppcboot.lds new file mode 100644 index 0000000..14ffc7f --- /dev/null +++ b/board/cray/L1/ppcboot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/cray/L1/init.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + ppc/zlib.o (.text) + +/*. = env_offset;*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cray/L1/ppcboot.lds.debug b/board/cray/L1/ppcboot.lds.debug new file mode 100644 index 0000000..122797c --- /dev/null +++ b/board/cray/L1/ppcboot.lds.debug @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index f7c7f6f..255bb78 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -26,12 +26,14 @@ #include #if defined(CONFIG_8xx) #include +#elif defined (CONFIG_405GP) +#include #endif - -#if defined(CONFIG_8xx) && (CONFIG_COMMANDS & CFG_CMD_REGINFO) +#if (CONFIG_COMMANDS & CFG_CMD_REGINFO) void do_reginfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +#if defined(CONFIG_8xx) volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; @@ -85,6 +87,92 @@ void do_reginfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) * May be some CPM info here? */ +/* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */ +#elif defined (CONFIG_405GP) + printf("\n405GP registers; MSR=%x\n",mfmsr()); + printf ("\nUniversal Interrupt Controller Regs\n" +"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr" +"\n" +"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + mfdcr(uicsr), + mfdcr(uicsrs), + mfdcr(uicer), + mfdcr(uiccr), + mfdcr(uicpr), + mfdcr(uictr), + mfdcr(uicmsr), + mfdcr(uicvr), + mfdcr(uicvcr)); + + printf ("\nMemory (SDRAM) Configuration\n" +"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); + + mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + + printf ("\n" +"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); + mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); + + printf ("\n\n" +"DMA Channels\n" +"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" +"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" +"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", +mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), +mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), +mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + + printf ( +"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" +"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", +mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), +mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + + printf ("\n" +"External Bus\n" +"pbear pbesr0 pbesr1 epcr\n"); + mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + + printf ("\n" +"pb0cr pb0ap pb1cr bp1ap pb2cr pb2ap pb3cr pb3ap\n"); + mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + + printf ("\n" +"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); + mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); + + printf ("\n\n"); +#endif /*(CONFIG_405GP)*/ } #endif /* CONFIG_8xx && CFG_CMD_REGINFO */ diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h index ff000f8..795cfee 100644 --- a/include/cmd_bsp.h +++ b/include/cmd_bsp.h @@ -135,12 +135,20 @@ void do_eecl (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); #endif /* CONFIG_HYMOD */ /* ----------------------------------------------------------------------------*/ +/* CRAY405 (L1) */ +#if defined (CONFIG_CRAYL1) +#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ + "L1cmd", 5, 4, 1, do_crayL1, \ + "L1cmd - L1 update, setup, commands \n", \ + "L1cmd update - update flash images from host\n" \ + "L1cmd boot - nfs or ramboot L1\n" \ +), +void do_crayL1 (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); +#endif /* CONFIG_CRAY405 */ +/* ----------------------------------------------------------------------------*/ #else - #define CMD_TBL_BSP - #endif /* CFG_CMD_BSP */ - #endif /* _CMD_BSP_H_ */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 919d5d0..162e08f 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -107,7 +107,10 @@ #define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 #define CONFIG_BOOTP_DNS 0x00000040 -#define CONFIG_BOOTP_ALL (~0) +#define CONFIG_BOOTP_VENDOREX 0x80000000 + +#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) + #define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ CONFIG_BOOTP_GATEWAY | \ diff --git a/include/cmd_reginfo.h b/include/cmd_reginfo.h index 248c59b..7784445 100644 --- a/include/cmd_reginfo.h +++ b/include/cmd_reginfo.h @@ -24,8 +24,8 @@ #ifndef _CMD_REGINFO_H_ #define _CMD_REGINFO_H_ -#if defined(CONFIG_8xx) && (CONFIG_COMMANDS & CFG_CMD_REGINFO) - +#if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \ + (CONFIG_COMMANDS & CFG_CMD_REGINFO) #define CMD_TBL_REGINFO MK_CMD_TBL_ENTRY( \ "reginfo", 3, 2, 1, do_reginfo, \ "reginfo - print register information\n", \ diff --git a/include/config_CRAYL1.h b/include/config_CRAYL1.h new file mode 100644 index 0000000..63c4dcc --- /dev/null +++ b/include/config_CRAYL1.h @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_CRAYL1 +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_PPC405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_PPC405 1 /* ...member of PPC405 family */ +#define CONFIG_BOARD_PRE_INIT 1 /* setup for 405gp */ +#define CONFIG_SYS_CLK_FREQ 25000000 /* .. frequency in L1 */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#undef CFG_ENV_IS_IN_NVRAM /* NO!use NVRAM for environment vars */ +#define CONFIG_MISC_INIT_R 1 /* call a misc_init when basic setup done, */ + /* in our case, make sure we have ethaddr */ + + + +/* Default environment stuff */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_AUTOLOAD "no" + +#define CONFIG_BOOTCOMMAND "setenv autostart no; "\ + "setenv autoload no; "\ + "dhcp; "\ + "L1cmd update; "\ + "L1cmd boot" + +#define CONFIG_PHY_ADDR 1 /* PHY address */ + + +#define CONFIG_COMMANDS (\ + CFG_CMD_BDI|\ + CFG_CMD_IMI|\ + CFG_CMD_FLASH|\ + CFG_CMD_MEMORY|\ + CFG_CMD_NET|\ + CFG_CMD_ENV|\ + CFG_CMD_CONSOLE|\ + CFG_CMD_ASKENV|\ + CFG_CMD_ECHO|\ + CFG_CMD_REGINFO|\ + CFG_CMD_DHCP|\ + CFG_CMD_DATE|\ + CFG_CMD_RUN|\ + CFG_CMD_BSP) + +#if LATER_ON + CFG_CMD_RUN + CFG_CMD_CACHE + CFG_CMD_EEPROM + CFG_CMD_I2C + CFG_CMD_IMMAP +#endif + + + +/* + * optional BOOTP fields + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_VENDOREX\ + |CONFIG_BOOTP_SUBNETMASK\ + |CONFIG_BOOTP_GATEWAY\ + |CONFIG_BOOTP_DNS\ + |CONFIG_BOOTP_HOSTNAME\ + |CONFIG_BOOTP_BOOTFILESIZE\ + |CONFIG_BOOTP_BOOTPATH) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_PCI /* DO NOT include pci support */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#undef CFG_KEY_REG_BASE_ADDR /* NO! peripherals... */ +#undef CFG_IR_REG_BASE_ADDR +#undef CFG_FPGA_REG_BASE_ADDR + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE 0xFFFE0040 + +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ +#define CFG_ENV_OFFSET 0x003D0000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ + +/* Memory tests: PPCBOOT relocates itself to the top of Ram, so its at + * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. + */ +#if 0 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#else + + +#define CFG_SDRAM_SIZE 32 /* megs of ram */ +#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ + /* the exception vector table */ + /* to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#undef CFG_NVRAM_BASE_ADDR + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + * DBU: we may yet use these someday.. + */ +#define EEPROM_WRITE_ADDRESS 0xA0 +#define EEPROM_READ_ADDRESS 0xA1 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/net/bootp.c b/net/bootp.c index ba0b54b..7a6d057 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -62,6 +62,12 @@ char *dhcpmsg2str(int type) default: return "UNKNOWN/INVALID MSG TYPE"; break; } } + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ +extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ +#endif + #endif static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) @@ -327,7 +333,7 @@ BootpTimeout(void) static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t RequestedIP) { u8 *start = e ; - u8 *cnt; + u8 *cnt, *x; *e++ = 99; /* RFC1048 Magic Cookie */ *e++ = 130; @@ -361,6 +367,11 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t Req *e++ = RequestedIP & 0xff; } +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if ((x = dhcp_vendorex_prep (e))) + return x - start ; +#endif + *e++ = 55; /* Parameter Request List */ cnt = e++; /* Pointer to count of requested items */ *cnt = 0; @@ -392,7 +403,6 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, IPaddr_t Req *e++ = 40; /* NIS Domain name request */ *cnt += 1; #endif - *e++ = 255; /* End of the list */ return e - start ; @@ -668,6 +678,10 @@ void DhcpOptionsProcess(char *popt) case 59: /* Ignore Rebinding Time Option */ break; default: +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if (dhcp_vendorex_proc(popt)) + break; +#endif printf("*** Unhandled DHCP Option in OFFER/ACK: %d\n", *popt); break; @@ -790,6 +804,8 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) debug ("DHCP State: REQUESTING\n"); if ( DhcpMessageType(bp->bp_vend) == DHCP_ACK ) { + char *s; + if ((*(uint *)bp->bp_vend) == BOOTP_VENDOR_MAGIC) DhcpOptionsProcess(&bp->bp_vend[4]); BootpCopyNetParams(bp); /* Store net params from reply */ @@ -797,10 +813,12 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) printf("DHCP client bound to address "); print_IPaddr(NetOurIP); printf("\n"); -#if 0 /* Not much point in configuring PPCBoot w/o loading boot file - CLH */ - NetState = NETLOOP_SUCCESS; - return; -#endif + + /* Obey the 'autoload' setting */ + if (((s = getenv("autoload")) != NULL) && (*s == 'n')) { + NetState = NETLOOP_SUCCESS; + return; + } /* Send ARP request to get TFTP server ethernet address. * This automagically starts TFTP, too. */