From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 4 Jun 2020 10:27:28 +0000 (+0800)
Subject: drm/amdgpu/mes10.1: add delay after mes engine enable
X-Git-Tag: howlett/maple/20220722_2~460^2~3^2~282
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=7149599be4085117ff21b2988890491fff25fecf;p=users%2Fjedix%2Flinux-maple.git

drm/amdgpu/mes10.1: add delay after mes engine enable

Add delay after mes engine enable, for it needs more time
to complete engine initialising.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 94812164998a..d4e64c5a3215 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -473,6 +473,7 @@ static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable)
 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 				     adev->enable_mes_kiq ? 1 : 0);
 		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
+		udelay(50);
 	} else {
 		data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);