From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 3 Nov 2023 20:07:39 +0000 (-1000)
Subject: Merge tag 'powerpc-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc... 
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=707df298cbde200b939c70be2577b20775fe3345;p=linux.git

Merge tag 'powerpc-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Michael Ellerman:

 - Add support for KVM running as a nested hypervisor under development
   versions of PowerVM, using the new PAPR nested virtualisation API

 - Add support for the BPF prog pack allocator

 - A rework of the non-server MMU handling to support execute-only on
   all platforms

 - Some optimisations & cleanups for the powerpc qspinlock code

 - Various other small features and fixes

Thanks to Aboorva Devarajan, Aditya Gupta, Amit Machhiwal, Benjamin
Gray, Christophe Leroy, Dr. David Alan Gilbert, Gaurav Batra, Gautam
Menghani, Geert Uytterhoeven, Haren Myneni, Hari Bathini, Joel Stanley,
Jordan Niethe, Julia Lawall, Kautuk Consul, Kuan-Wei Chiu, Michael
Neuling, Minjie Du, Muhammad Muzammil, Naveen N Rao, Nicholas Piggin,
Nick Child, Nysal Jan K.A, Peter Lafreniere, Rob Herring, Sachin Sant,
Sebastian Andrzej Siewior, Shrikanth Hegde, Srikar Dronamraju, Stanislav
Kinsburskii, Vaibhav Jain, Wang Yufen, Yang Yingliang, and Yuan Tan.

* tag 'powerpc-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (100 commits)
  powerpc/vmcore: Add MMU information to vmcoreinfo
  Revert "powerpc: add `cur_cpu_spec` symbol to vmcoreinfo"
  powerpc/bpf: use bpf_jit_binary_pack_[alloc|finalize|free]
  powerpc/bpf: rename powerpc64_jit_data to powerpc_jit_data
  powerpc/bpf: implement bpf_arch_text_invalidate for bpf_prog_pack
  powerpc/bpf: implement bpf_arch_text_copy
  powerpc/code-patching: introduce patch_instructions()
  powerpc/32s: Implement local_flush_tlb_page_psize()
  powerpc/pseries: use kfree_sensitive() in plpks_gen_password()
  powerpc/code-patching: Perform hwsync in __patch_instruction() in case of failure
  powerpc/fsl_msi: Use device_get_match_data()
  powerpc: Remove cpm_dp...() macros
  powerpc/qspinlock: Rename yield_propagate_owner tunable
  powerpc/qspinlock: Propagate sleepy if previous waiter is preempted
  powerpc/qspinlock: don't propagate the not-sleepy state
  powerpc/qspinlock: propagate owner preemptedness rather than CPU number
  powerpc/qspinlock: stop queued waiters trying to set lock sleepy
  powerpc/perf: Fix disabling BHRB and instruction sampling
  powerpc/trace: Add support for HAVE_FUNCTION_ARG_ACCESS_API
  powerpc/tools: Pass -mabi=elfv2 to gcc-check-mprofile-kernel.sh
  ...
---

707df298cbde200b939c70be2577b20775fe3345
diff --cc Documentation/arch/powerpc/kvm-nested.rst
index 000000000000,630602a8aa00..630602a8aa00
mode 000000,100644..100644
--- a/Documentation/arch/powerpc/kvm-nested.rst
+++ b/Documentation/arch/powerpc/kvm-nested.rst
diff --cc arch/powerpc/mm/pgtable.c
index 4d69bfb9bc11,79508c1d15d7..a04ae4449a02
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@@ -104,10 -104,8 +104,10 @@@ static pte_t set_pte_filter_hash(pte_t 
  /* Embedded type MMU with HW exec support. This is a bit more complicated
   * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
   * instead we "filter out" the exec permission for non clean pages.
 + *
 + * This is also called once for the folio. So only work with folio->flags here.
   */
- static inline pte_t set_pte_filter(pte_t pte)
+ static inline pte_t set_pte_filter(pte_t pte, unsigned long addr)
  {
  	struct folio *folio;
  
@@@ -195,26 -193,18 +195,26 @@@ void set_ptes(struct mm_struct *mm, uns
  
  	/* Note: mm->context.id might not yet have been assigned as
  	 * this context might not have been activated yet when this
 -	 * is called.
 +	 * is called. Filter the pte value and use the filtered value
 +	 * to setup all the ptes in the range.
  	 */
- 	pte = set_pte_filter(pte);
+ 	pte = set_pte_filter(pte, addr);
  
 -	/* Perform the setting of the PTE */
 -	arch_enter_lazy_mmu_mode();
 +	/*
 +	 * We don't need to call arch_enter/leave_lazy_mmu_mode()
 +	 * because we expect set_ptes to be only be used on not present
 +	 * and not hw_valid ptes. Hence there is no translation cache flush
 +	 * involved that need to be batched.
 +	 */
  	for (;;) {
 +
 +		/*
 +		 * Make sure hardware valid bit is not set. We don't do
 +		 * tlb flush for this update.
 +		 */
 +		VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
 +
 +		/* Perform the setting of the PTE */
  		__set_pte_at(mm, addr, ptep, pte, 0);
  		if (--nr == 0)
  			break;