From: John Fastabend Date: Wed, 21 Sep 2011 14:44:10 +0000 (+0000) Subject: ixgbe: X540 devices RX PFC frames pause traffic even if disabled X-Git-Tag: v2.6.39-400.9.0~423^2~19^2~11^2~154 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=7015da5d25d2a2167ce29c8b01e605c086e4abd9;p=users%2Fjedix%2Flinux-maple.git ixgbe: X540 devices RX PFC frames pause traffic even if disabled Receiving PFC (priority flow control) frames while the feature is off should not pause the traffic class. On the X540 devices the traffic class react to frames if it was previously enabled because the field is incorrectly cleared. (cherry picked from commit 6b8456c0199c4dd35bb7a04ff299ab925699e390) Signed-off-by: John Fastabend Tested-by: Ross Brattain Signed-off-by: Jeff Kirsher Signed-off-by: Joe Jin --- diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c index 45fe71030455..32cd97bc794d 100644 --- a/drivers/net/ixgbe/ixgbe_dcb_82599.c +++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c @@ -271,13 +271,23 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF; if (hw->mac.type == ixgbe_mac_X540) { - reg &= ~(IXGBE_MFLCN_RPFCE_MASK | 0x10); + reg &= ~IXGBE_MFLCN_RPFCE_MASK; reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; } IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); } else { + /* X540 devices have a RX bit that should be cleared + * if PFC is disabled on all TCs but PFC features is + * enabled. + */ + if (hw->mac.type == ixgbe_mac_X540) { + reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); + reg &= ~IXGBE_MFLCN_RPFCE_MASK; + IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); + } + for (i = 0; i < MAX_TRAFFIC_CLASS; i++) hw->mac.ops.fc_enable(hw, i); } diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index f9c48501a743..fbb5f1220f34 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h @@ -1848,7 +1848,7 @@ enum { #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ -#define IXGBE_MFLCN_RPFCE_MASK 0x00000FE0 /* Receive FC Mask */ +#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Receive FC Mask */ #define IXGBE_MFLCN_RPFCE_SHIFT 4