From: Chuan Liu Date: Mon, 9 Sep 2024 10:08:57 +0000 (+0800) Subject: clk: meson: c3: pll: fix frac maximum value for hifi_pll X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=6e442c2d7825a0758f00610d94822cfa82a258b9;p=users%2Fwilly%2Fxarray.git clk: meson: c3: pll: fix frac maximum value for hifi_pll The fractional denominator of C3's hifi_pll fractional multiplier is fixed to 100000. Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock") Signed-off-by: Chuan Liu Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com Signed-off-by: Jerome Brunet --- diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index 32bd2ed9d304..35fda31a19e2 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = { .range = &c3_gp0_pll_mult_range, .init_regs = c3_hifi_init_regs, .init_count = ARRAY_SIZE(c3_hifi_init_regs), + .frac_max = 100000, }, .hw.init = &(struct clk_init_data) { .name = "hifi_pll_dco",