From: Tim Harvey Date: Thu, 5 Sep 2024 18:32:28 +0000 (-0700) Subject: arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=6a5d95b06d93ebf40f0df9b9c23c923912b0d494;p=users%2Fwilly%2Fxarray.git arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the GPIO10 pin of the M.2 socket for compatibility with certain devices. Add the iomux and a line name for this. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index d765b7972841..9885948952b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -299,7 +299,7 @@ &gpio3 { gpio-line-names = "", "", "", "", "", "", "m2_rst", "", - "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "m2_gpio10", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -816,6 +816,7 @@ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */