From: Bjorn Helgaas <bhelgaas@google.com>
Date: Thu, 27 Mar 2025 18:14:51 +0000 (-0500)
Subject: Merge branch 'pci/controller/qcom'
X-Git-Tag: nvme-6.15-2025-04-02~45^2~4
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=6547faa1bc25c4392473b80615cc30088295c89c;p=nvme.git

Merge branch 'pci/controller/qcom'

- Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as
  RESERVED (Manivannan Sadhasivam)

- Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry
  Baryshkov)

- Make DT iommu property required for SA8775P and prohibited for SDX55
  (Dmitry Baryshkov)

- Add DT iommu and DMA-related properties for Qualcomm SM8450 (Dmitry
  Baryshkov)

- Consolidate DMA vs non-DMA cases in DT (Dmitry Baryshkov)

- Add endpoint DT properties for SAR2130P and enable endpoint mode in
  driver (Dmitry Baryshkov)

* pci/controller/qcom:
  PCI: qcom-ep: Enable EP mode support for SAR2130P
  dt-bindings: PCI: qcom-ep: Add SAR2130P compatible
  dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases
  dt-bindings: PCI: qcom-ep: Enable DMA for SM8450
  dt-bindings: PCI: qcom-ep: Describe optional IOMMU
  dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property
  PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED
---

6547faa1bc25c4392473b80615cc30088295c89c