From: Claudiu Beznea Date: Fri, 6 Dec 2024 11:13:35 +0000 (+0200) Subject: iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=645fb7c22fd8d27c223b0e4abff442632bd9a75a;p=users%2Fjedix%2Flinux-maple.git iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP include: - 9 channels, with one dedicated to reading the temperature reported by the Thermal Sensor Unit (TSU) - A different default ADCMP value, which is written to the ADM3 register. - Different default sampling rates - ADM3.ADSMP field is 8 bits wide - ADINT.INTEN field is 11 bits wide Signed-off-by: Claudiu Beznea Link: https://patch.msgid.link/20241206111337.726244-14-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Jonathan Cameron --- diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index ad5c403b0c67..883c167c0670 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -504,7 +504,16 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = { .adivc = true }; +static const struct rzg2l_adc_hw_params rzg3s_hw_params = { + .num_channels = 9, + .default_adcmp = 0x1d, + .default_adsmp = { 0x7f, 0xff }, + .adsmp_mask = GENMASK(7, 0), + .adint_inten_mask = GENMASK(11, 0), +}; + static const struct of_device_id rzg2l_adc_match[] = { + { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params }, { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params }, { /* sentinel */ } };