From: wdenk Date: Thu, 14 Feb 2002 09:25:54 +0000 (+0000) Subject: * Fix flash code for PCIPPC2/PCIPPC6 boards X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=5d53928b96c335a62695d407161df050ff63e17c;p=users%2Frw%2Fppcboot.git * Fix flash code for PCIPPC2/PCIPPC6 boards (cannot use unlock bypas mode on Am29F040B) * Add configuration for PCIPPC6 board (with SCSI support) * Fix HUSH parser problem qwith scripts --- diff --git a/CHANGELOG b/CHANGELOG index 5864f47..b158853 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,13 @@ Modifications for 1.1.5: ====================================================================== +* Fix flash code for PCIPPC2/PCIPPC6 boards + (cannot use unlock bypas mode on Am29F040B) + +* Add configuration for PCIPPC6 board (with SCSI support) + +* Fix HUSH parser problem qwith scripts + * Fix output for CFG_FLASH_CHECKSUM (based on patch by Greg Allen, 12 Feb 2002 diff --git a/CREDITS b/CREDITS index a69b410..43edb33 100644 --- a/CREDITS +++ b/CREDITS @@ -22,6 +22,10 @@ N: Swen Anderson E: sand@peppercon.de D: ERIC Support +N: Guillaume Alexandre +E: guillaume.alexandre@gespac.ch +D: Add PCIPPC6 configuration + N: Pierre Aubert E: D: Support for RPXClassic board diff --git a/MAKEALL b/MAKEALL index 756e40c..b1b1716 100755 --- a/MAKEALL +++ b/MAKEALL @@ -63,7 +63,7 @@ LIST_8260=" \ ######################################################################### LIST_74xx=" \ - EVB64260 PCIPPC2 ZUMA \ + EVB64260 PCIPPC2 PCIPPC6 ZUMA \ " ######################################################################### diff --git a/Makefile b/Makefile index 385a669..81367d8 100644 --- a/Makefile +++ b/Makefile @@ -724,7 +724,8 @@ ZUMA_config: unconfig echo "CPU = 74xx_7xx" >>config.mk ; \ echo "#include " >config.h -PCIPPC2_config: unconfig +PCIPPC2_config \ +PCIPPC6_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd include ; \ echo "ARCH = ppc" > config.mk ; \ diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile index 74caceb..203723b 100644 --- a/board/pcippc2/Makefile +++ b/board/pcippc2/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o eepro100.o pci.o \ - fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o + fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o sym53c8xx.o AOBJS = OBJS = $(COBJS) $(AOBJS) diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c index 877f0e5..7125e1f 100644 --- a/board/pcippc2/flash.c +++ b/board/pcippc2/flash.c @@ -29,19 +29,27 @@ #include #include +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -static ulong flash_get_size (u32 addr, flash_info_t *info); -static int flash_get_offsets (u32 base, flash_info_t *info); +static ulong flash_get_size (ulong addr, flash_info_t *info); +static int flash_get_offsets (ulong base, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (u32 addr); +static void flash_reset (ulong addr); unsigned long flash_init (void) { unsigned int i; unsigned long flash_size = 0; - unsigned long bank_size; - unsigned int bank = 0; /* Init: no FLASHes known */ for (i=0; i= CFG_FLASH_BASE && \ CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - flash_info + bank); + &flash_info[0]); #endif #ifdef CFG_ENV_IS_IN_FLASH @@ -72,11 +79,9 @@ unsigned long flash_init (void) flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - flash_info + bank); + &flash_info[0]); #endif - flash_size += bank_size; - bank++; } else { puts ("Warning: the BOOT Flash is not initialised !"); } @@ -87,7 +92,7 @@ unsigned long flash_init (void) /* * The following code cannot be run from FLASH! */ -static ulong flash_get_size (u32 addr, flash_info_t *info) +static ulong flash_get_size (ulong addr, flash_info_t *info) { short i; uchar value; @@ -102,6 +107,9 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) value = in8(addr); iobarrier_rw(); + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); + switch (value | (value << 16)) { case AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; @@ -113,6 +121,8 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) default: info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; flash_reset (addr); return 0; } @@ -120,56 +130,67 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) value = in8(addr + 1); /* device ID */ iobarrier_rw(); + DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); + switch (value) { case AMD_ID_F040B: + DEBUGF("Am29F040B\n"); info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x00080000; break; /* => 512 kB */ case AMD_ID_LV040B: + DEBUGF("Am29LV040B\n"); info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x00080000; break; /* => 512 kB */ case AMD_ID_LV400T: + DEBUGF("Am29LV400T\n"); info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00100000; break; /* => 1 MB */ case AMD_ID_LV400B: + DEBUGF("Am29LV400B\n"); info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00100000; break; /* => 1 MB */ case AMD_ID_LV800T: + DEBUGF("Am29LV800T\n"); info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00200000; break; /* => 2 MB */ case AMD_ID_LV800B: + DEBUGF("Am29LV400B\n"); info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00200000; break; /* => 2 MB */ case AMD_ID_LV160T: + DEBUGF("Am29LV160T\n"); info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00400000; break; /* => 4 MB */ case AMD_ID_LV160B: + DEBUGF("Am29LV160B\n"); info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00400000; break; /* => 4 MB */ case AMD_ID_LV320T: + DEBUGF("Am29LV320T\n"); info->flash_id += FLASH_AM320T; info->sector_count = 67; info->size = 0x00800000; @@ -178,6 +199,7 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) #if 0 /* Has the same ID as AMD_ID_LV320T, to be fixed */ case AMD_ID_LV320B: + DEBUGF("Am29LV320B\n"); info->flash_id += FLASH_AM320B; info->sector_count = 67; info->size = 0x00800000; @@ -185,6 +207,7 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) #endif case AMD_ID_LV033C: + DEBUGF("Am29LV033C\n"); info->flash_id += FLASH_AM033C; info->sector_count = 64; info->size = 0x01000000; @@ -196,6 +219,12 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) } + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + if (! flash_get_offsets (addr, info)) { flash_reset (addr); return 0; @@ -218,7 +247,7 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) return (info->size); } -static int flash_get_offsets (u32 base, flash_info_t *info) +static int flash_get_offsets (ulong base, flash_info_t *info) { unsigned int i; @@ -239,7 +268,7 @@ static int flash_get_offsets (u32 base, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile u32 addr = info->start[0]; + volatile ulong addr = info->start[0]; int flag, prot, sect, l_sect; ulong start, now, last; @@ -315,9 +344,13 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; addr = info->start[l_sect]; + + DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + while ((in8(addr) & 0x80) != 0x80) { if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); + flash_reset (info->start[0]); return 1; } /* show that we're waiting */ @@ -414,63 +447,52 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { - volatile u32 addr = info->start[0]; + volatile ulong addr = info->start[0]; ulong start; - int flag, i; + int i; /* Check if Flash is (sufficiently) erased */ if ((in32(dest) & data) != data) { return (2); } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x20); - iobarrier_rw(); /* write each byte out */ for (i = 0; i < 4; i++) { char *data_ch = (char *)&data; - out8(addr, 0xA0); + int flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0xA0); iobarrier_rw(); out8(dest+i, data_ch[i]); iobarrier_rw(); - udelay(10); /* XXX */ - } - /* we're done, now do an unlock bypass reset */ - out8(addr, 0x90); - iobarrier_rw(); - out8(addr, 0x00); - iobarrier_rw(); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); + /* data polling for D7 */ + start = get_timer (0); + while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flash_reset (addr); + return (1); + } + iobarrier_rw(); } - iobarrier_rw(); } flash_reset (addr); - return (0); } /* * Reset bank to read mode */ -static void flash_reset (u32 addr) +static void flash_reset (ulong addr) { out8(addr, 0xF0); /* reset bank */ iobarrier_rw(); diff --git a/board/pcippc2/pci.c b/board/pcippc2/pci.c index 6756ffd..a99917d 100644 --- a/board/pcippc2/pci.c +++ b/board/pcippc2/pci.c @@ -208,6 +208,16 @@ void PCI_Config_Device(int BusDevFunc, int NumBaseAddr) printf(" PCI memory addr = 0x%lx\n", AddrProg); #endif LowestMemAddr = AddrProg + AddrDesc; + + /* Check 64 bit BAR */ + if ((PCI_Read_CFG_Reg (BusDevFunc, + PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), + 4) & 0x6 ) == 0x4) { + AddrSlot++; + PCI_Write_CFG_Reg (BusDevFunc, + PCI_CFG_BASE_ADDRESS_0 + (4*AddrSlot), + 0x0, 4); + } } } diff --git a/board/pcippc2/sym53c8xx.c b/board/pcippc2/sym53c8xx.c new file mode 100644 index 0000000..24d28a4 --- /dev/null +++ b/board/pcippc2/sym53c8xx.c @@ -0,0 +1,801 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * partly derived from + * linux/drivers/scsi/sym53c8xx.c + * + */ + +/* + * SCSI support based on the chip sym53C810. + * + * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH + * The local version of this driver for the BAB750 board does not + * use interrupts but polls the chip instead (see the call of + * 'handle_scsi_int()' in 'scsi_issue()'. + */ + +#include +#include +#include + +// #include +#include "pci.h" +#include "cpc710_pci.h" + +#include +#include "sym53c8xx.h" + +#include + + +unsigned long phys_to_bus(void *address) +{ + return (unsigned long) pci_ram_to_mem ((u32) address); +} + +void * bus_to_phys(unsigned long address) +{ + return (void *) pci_mem_to_phys ((u32) address); +} + + +#undef SYM53C8XX_DEBUG + +#ifdef SYM53C8XX_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) + + +#undef SCSI_SINGLE_STEP +/* + * Single Step is only used for debug purposes + */ +#ifdef SCSI_SINGLE_STEP +static unsigned long start_script_select; +static unsigned long start_script_msgout; +static unsigned long start_script_msgin; +static unsigned long start_script_msg_ext; +static unsigned long start_script_cmd; +static unsigned long start_script_data_in; +static unsigned long start_script_data_out; +static unsigned long start_script_status; +static unsigned long start_script_complete; +static unsigned long start_script_error; +static unsigned long start_script_reselection; +static unsigned int len_script_select; +static unsigned int len_script_msgout; +static unsigned int len_script_msgin; +static unsigned int len_script_msg_ext; +static unsigned int len_script_cmd; +static unsigned int len_script_data_in; +static unsigned int len_script_data_out; +static unsigned int len_script_status; +static unsigned int len_script_complete; +static unsigned int len_script_error; +static unsigned int len_script_reselection; +#endif + + +static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ +static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ +static unsigned long script_select[8]; /* script for selection */ +static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ +static unsigned long script_msgin[14]; /* script for message in phase */ +static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ +static unsigned long script_cmd[18]; /* script for command phase */ +static unsigned long script_data_in[8]; /* script for data in phase */ +static unsigned long script_data_out[8]; /* script for data out phase */ +static unsigned long script_status[6]; /* script for status phase */ +static unsigned long script_complete[10]; /* script for complete */ +static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ +static unsigned long script_error[2]; /* script for error handling */ + +static unsigned long int_stat[3]; /* interrupt status */ +static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ + + +#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ + +#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ +#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ + +/********************************************************************************* + * forward declerations + */ + +void scsi_chip_init(void); +void handle_scsi_int(void); + + +/******************************************************************************** + * reports SCSI errors to the user + */ +void scsi_print_error(ccb *pccb) +{ + int i; + printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); + printf(" CCB: "); + for(i=0;icmdlen;i++) + printf("%02X ",pccb->cmd[i]); + printf("(len=%d)\n",pccb->cmdlen); + printf(" Cntrl: "); + switch(pccb->contr_stat) { + case SIR_COMPLETE: printf("Complete (no Error)\n"); break; + case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; + case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; + case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; + case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; + case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; + case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; + case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; + case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; + case INT_ON_FY: printf("Interrupt on fly\n"); break; + case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; + case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; + case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; + case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; + default: printf("unknown status %lx\n",pccb->contr_stat); break; + } + printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: printf("No Sense)"); break; + case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; + case SENSE_NOT_READY: printf("Not Ready)"); break; + case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; + case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; + case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; + case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; + case SENSE_DATA_PROTECT: printf("Data Protect)"); break; + case SENSE_BLANK_CHECK: printf("Blank check)"); break; + case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; + case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; + case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; + case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; + case SENSE_MISCOMPARE: printf("Misscompare\n"); break; + default: printf("Illegal Sensecode\n"); break; + } + printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); + printf(" Status: "); + switch(pccb->status) { + case S_GOOD : printf("Good\n"); break; + case S_CHECK_COND: printf("Check condition\n"); break; + case S_COND_MET: printf("Condition Met\n"); break; + case S_BUSY: printf("Busy\n"); break; + case S_INT: printf("Intermediate\n"); break; + case S_INT_COND_MET: printf("Intermediate condition met\n"); break; + case S_CONFLICT: printf("Reservation conflict\n"); break; + case S_TERMINATED: printf("Command terminated\n"); break; + case S_QUEUE_FULL: printf("Task set full\n"); break; + default: printf("unknown: %02X\n",pccb->status); break; + } + +} + + + +/****************************************************************************** + * sets-up the SCSI controller + * the base memory address is retrived via the PCI_Read_CFG_Reg + */ +void scsi_low_level_init(int busdevfunc) +{ + unsigned long cmd; + unsigned long addr; + unsigned char vec; + vec=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_DEV_INT_LINE, 1); + addr= (unsigned long) bus_to_phys( (u32) PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_BASE_ADDRESS_1, 4) & ~0xF ); + + /* + * Enable bus mastering in case this has not been done, yet. + */ + cmd=PCI_Read_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, 4); + cmd |= PCI_CMD_MASTER; + PCI_Write_CFG_Reg(busdevfunc, PCI_CFG_COMMAND, cmd, 4); + + scsi_mem_addr=addr; + scsi_chip_init(); + scsi_bus_reset(); +} + + +/************************************************************************************ + * Low level Part of SCSI Driver + */ + +/* + * big-endian -> little endian conversion for the script + */ +unsigned long swap_script(unsigned long val) +{ + unsigned long tmp; + tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); + return tmp; +} + + +void scsi_write_byte(ulong offset,unsigned char val) +{ + out8(scsi_mem_addr+offset,val); +} + + +unsigned char scsi_read_byte(ulong offset) +{ + return(in8(scsi_mem_addr+offset)); +} + + +/******************************************************************************** + * interrupt handler + */ +void handle_scsi_int(void) +{ + unsigned char stat,stat1,stat2; + unsigned short sstat; + int i; +#ifdef SCSI_SINGLE_STEP + unsigned long tt; +#endif + stat=scsi_read_byte(ISTAT); + if((stat & DIP)==DIP) { /* DMA Interrupt pending */ + stat1=scsi_read_byte(DSTAT); +#ifdef SCSI_SINGLE_STEP + if((stat1 & SSI)==SSI) + { + tt=in32r(scsi_mem_addr+DSP); + if(((tt)>=start_script_select) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgout) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgin) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msg_ext) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_cmd) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_in) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_out) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_status) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_complete) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_error) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_reselection) && ((tt)>2); + goto end_single; + } + printf("sc: %lx\n",tt); +end_single: + stat2=scsi_read_byte(DCNTL); + stat2|=STD; + scsi_write_byte(DCNTL,stat2); + } +#endif + if((stat1 & SIR)==SIR) /* script interrupt */ + { + int_stat[0]=in32(scsi_mem_addr+DSPS); + } + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & SIP)==SIP) { /* scsi interrupt */ + sstat = (unsigned short)scsi_read_byte(SIST+1); + sstat <<=8; + sstat |= (unsigned short)scsi_read_byte(SIST); + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=SCSI_INT_STATE | sstat; + stat1=scsi_read_byte(DSTAT); + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & INTF)==INTF) { /* interrupt on Fly */ + scsi_write_byte(ISTAT,stat); /* clear it */ + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=INT_ON_FY; + } +} + +void scsi_bus_reset(void) +{ + unsigned char t; + int i; + int end = CFG_SCSI_SPIN_UP_TIME*1000; + + t=scsi_read_byte(SCNTL1); + scsi_write_byte(SCNTL1,(t | CRST)); + udelay(50); + scsi_write_byte(SCNTL1,t); + + puts("waiting for devices to spin up"); + for(i=0;i>8)); + scsi_write_byte(DIEN,script_int_mask); +} + +void scsi_write_dsp(unsigned long start) +{ + unsigned long val; +#ifdef SCSI_SINGLE_STEP + unsigned char t; +#endif + val = start; + out32r(scsi_mem_addr + DSP,start); +#ifdef SCSI_SINGLE_STEP + t=scsi_read_byte(DCNTL); + t|=STD; + scsi_write_byte(DCNTL,t); +#endif +} + +/* only used for debug purposes */ +void scsi_print_script(void) +{ + printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); + printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); + printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); + printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); + printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); + printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); + printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); + printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); + printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); + printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); +} + + + +void scsi_set_script(ccb *pccb) +{ + int i; + i=0; + script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); + script_select[i++]=0; /* LED ON */ + script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ + script_select[i++]=0; + /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ + script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); + script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ + script_select[i++]=swap_script(SCR_JUMP); /* next section */ + /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ + script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ + +#ifdef SCSI_SINGLE_STEP + start_script_select=(unsigned long)&script_select[0]; + len_script_select=i*4; +#endif + + i=0; + script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); + script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; + script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); + script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); + script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ + script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ + script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_msgout[i++]=SIR_MSG_OUT_NO_CMD; + +#ifdef SCSI_SINGLE_STEP + start_script_msgout=(unsigned long)&script_msgout[0]; + len_script_msgout=i*4; +#endif + i=0; + script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); + script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_cmd[i++]=SIR_CMD_OUT_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_cmd=(unsigned long)&script_cmd[0]; + len_script_cmd=i*4; +#endif + i=0; + script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ + script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_out[i++]=swap_script(SCR_INT); + script_data_out[i++]=SIR_DATA_OUT_ERR; + +#ifdef SCSI_SINGLE_STEP + start_script_data_out=(unsigned long)&script_data_out[0]; + len_script_data_out=i*4; +#endif + i=0; + script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ + script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_in[i++]=swap_script(SCR_INT); + script_data_in[i++]=SIR_DATA_IN_ERR; +#ifdef SCSI_SINGLE_STEP + start_script_data_in=(unsigned long)&script_data_in[0]; + len_script_data_in=i*4; +#endif + i=0; + script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); + script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); + script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); + script_msgin[i++]=swap_script(SCR_INT); + script_msgin[i++]=SIR_MSG_RECEIVED; +#ifdef SCSI_SINGLE_STEP + start_script_msgin=(unsigned long)&script_msgin[0]; + len_script_msgin=i*4; +#endif + i=0; + script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ + script_msg_ext[i++]=0; + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_INT); + script_msg_ext[i++]=SIR_MSG_OVER7; +#ifdef SCSI_SINGLE_STEP + start_script_msg_ext=(unsigned long)&script_msg_ext[0]; + len_script_msg_ext=i*4; +#endif + i=0; + script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); + script_status[i++]=swap_script(phys_to_bus(&pccb->status)); + script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); + script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_status[i++]=swap_script(SCR_INT); + script_status[i++]=SIR_STATUS_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_status=(unsigned long)&script_status[0]; + len_script_status=i*4; +#endif + i=0; + script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_WAIT_DISC); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); + script_complete[i++]=0; /* LED OFF */ + script_complete[i++]=swap_script(SCR_INT); + script_complete[i++]=SIR_COMPLETE; +#ifdef SCSI_SINGLE_STEP + start_script_complete=(unsigned long)&script_complete[0]; + len_script_complete=i*4; +#endif + i=0; + script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ + script_error[i++]=SIR_SCRIPT_ERROR; +#ifdef SCSI_SINGLE_STEP + start_script_error=(unsigned long)&script_error[0]; + len_script_error=i*4; +#endif + i=0; + script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ + script_reselection[i++]=0; + script_reselection[i++]=swap_script(SCR_WAIT_RESEL); + script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ +#ifdef SCSI_SINGLE_STEP + start_script_reselection=(unsigned long)&script_reselection[0]; + len_script_reselection=i*4; +#endif +} + + + +void scsi_issue(ccb *pccb) +{ + int i; + unsigned short sstat; + int retrycnt; /* retry counter */ + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + /* struct pccb must be set-up correctly */ + retrycnt=0; + PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); + pccb->trans_bytes=0; /* no bytes transfered yet */ + scsi_set_script(pccb); /* fill in SCRIPT */ + scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ + script_int_mask=0xff; /* enable all Ints */ + scsi_int_enable(); + scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ + /* now we have to wait for IRQs */ +retry: + /* + * This version of the driver is _not_ interrupt driven, + * but polls the chip's interrupt registers (ISTAT, DSTAT). + */ + while(int_stat[0]==0) + handle_scsi_int(); + + if(int_stat[0]==SIR_COMPLETE) { + if(pccb->msgin[0]==M_DISCONNECT) { + PRINTF("Wait for reselection\n"); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ + goto retry; + } + pccb->contr_stat=SIR_COMPLETE; + return; + } + if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ + sstat=(unsigned short)int_stat[0]; + if((sstat & STO)==STO) { /* selection timeout */ + pccb->contr_stat=SCSI_SEL_TIME_OUT; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Selection Timeout\n",pccb->target); + return; + } + if((sstat & UDC)==UDC) { /* unexpected disconnect */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if((sstat & RSL)==RSL) { /* reselection */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ + if(retrycnttrans_bytes=pccb->datalen - + ((unsigned long)scsi_read_byte(DBC) | + ((unsigned long)scsi_read_byte(DBC+1)<<8) | + ((unsigned long)scsi_read_byte(DBC+2)<<16)); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + retrycnt++; + PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", + pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); + scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ + goto retry; + } + if((sstat & MA)==MA) + pccb->contr_stat=SCSI_MA_TIME_OUT; + else + pccb->contr_stat=SCSI_HNS_TIME_OUT; + PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); + return; + } /* no phase int */ +/* if((sstat & CMP)==CMP) { + pccb->contr_stat=SIR_COMPLETE; + return; + } +*/ + PRINTF("SCSI INT %lX\n",int_stat[0]); + pccb->contr_stat=int_stat[0]; + return; + } /* end scsi int */ + PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); + pccb->contr_stat=int_stat[0]; + return; +} + +int scsi_exec(ccb *pccb) +{ + unsigned char tmpcmd[16],tmpstat; + int i,retrycnt,t; + unsigned long transbytes,datalen; + unsigned char *tmpptr; + retrycnt=0; +retry: + scsi_issue(pccb); + if(pccb->contr_stat!=SIR_COMPLETE) + return FALSE; + if(pccb->status==S_GOOD) + return TRUE; + if(pccb->status==S_CHECK_COND) { /* check condition */ + for(i=0;i<16;i++) + tmpcmd[i]=pccb->cmd[i]; + pccb->cmd[0]=SCSI_REQ_SENSE; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=14; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; + transbytes=pccb->trans_bytes; + tmpptr=pccb->pdata; + pccb->pdata=&pccb->sense_buf[0]; + datalen=pccb->datalen; + pccb->datalen=14; + tmpstat=pccb->status; + scsi_issue(pccb); + for(i=0;i<16;i++) + pccb->cmd[i]=tmpcmd[i]; + pccb->trans_bytes=transbytes; + pccb->pdata=tmpptr; + pccb->datalen=datalen; + pccb->status=tmpstat; + PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, + pccb->sense_buf[12],pccb->sense_buf[13]); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: + case SENSE_RECOVERED_ERROR: + /* seems to be ok */ + return TRUE; + break; + case SENSE_NOT_READY: + if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { + /* if device is not in process of becoming ready */ + return FALSE; + break; + } /* else fall through */ + case SENSE_UNIT_ATTENTION: + if(retrycnttarget,retrycnt); + for(t=0;ttarget,retrycnt); + return FALSE; + default: + return FALSE; + } + } + PRINTF("Status = %X\n",pccb->status); + return FALSE; +} + + + + +void scsi_chip_init(void) +{ + /* first we issue a soft reset */ + scsi_write_byte(ISTAT,SRST); + udelay(1000); + scsi_write_byte(ISTAT,0); + /* setup chip */ + scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ + scsi_write_byte(SCNTL1,0x00); + scsi_write_byte(SCNTL2,0x00); + scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ + scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ + scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ + scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ + scsi_int_mask=0x0000; /* no Interrupt is enabled */ + script_int_mask=0x00; + scsi_int_enable(); + scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ + scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ + scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ + scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ + scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ + scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ + scsi_write_byte(STEST3,0x80); /* enable tolerANT */ + scsi_write_byte(CTEST3,0x04); /* clear FIFO */ + scsi_write_byte(CTEST4,0x00); + scsi_write_byte(CTEST5,0x00); +#ifdef SCSI_SINGLE_STEP +/* scsi_write_byte(DCNTL,IRQM | SSM); */ + scsi_write_byte(DCNTL,IRQD | SSM); + scsi_write_byte(DMODE,MAN); +#else +/* scsi_write_byte(DCNTL,IRQM); */ + scsi_write_byte(DCNTL,IRQD); + scsi_write_byte(DMODE,0x00); +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ + + diff --git a/board/pcippc2/sym53c8xx.h b/board/pcippc2/sym53c8xx.h new file mode 100644 index 0000000..32a78f0 --- /dev/null +++ b/board/pcippc2/sym53c8xx.h @@ -0,0 +1,583 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Most of these definitions are derived from + * linux/drivers/scsi/sym53c8xx_defs.h + * + */ + +#ifndef _SYM53C8XX_DEFS_H +#define _SYM53C8XX_DEFS_H + + +#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ + +#define SCNTL1 0x01 /* no reset */ + #define ISCON 0x10 /* connected to scsi */ + #define CRST 0x08 /* force reset */ + #define IARB 0x02 /* immediate arbitration */ + +#define SCNTL2 0x02 /* no disconnect expected */ + #define SDU 0x80 /* cmd: disconnect will raise error */ + #define CHM 0x40 /* sta: chained mode */ + #define WSS 0x08 /* sta: wide scsi send [W]*/ + #define WSR 0x01 /* sta: wide scsi received [W]*/ + +#define SCNTL3 0x03 /* cnf system clock dependent */ + #define EWS 0x08 /* cmd: enable wide scsi [W]*/ + #define ULTRA 0x80 /* cmd: ULTRA enable */ + /* bits 0-2, 7 rsvd for C1010 */ + +#define SCID 0x04 /* cnf host adapter scsi address */ + #define RRE 0x40 /* r/w:e enable response to resel. */ + #define SRE 0x20 /* r/w:e enable response to select */ + +#define SXFER 0x05 /* ### Sync speed and count */ + /* bits 6-7 rsvd for C1010 */ + +#define SDID 0x06 /* ### Destination-ID */ + +#define GPREG 0x07 /* ??? IO-Pins */ + +#define SFBR 0x08 /* ### First byte in phase */ + +#define SOCL 0x09 + #define CREQ 0x80 /* r/w: SCSI-REQ */ + #define CACK 0x40 /* r/w: SCSI-ACK */ + #define CBSY 0x20 /* r/w: SCSI-BSY */ + #define CSEL 0x10 /* r/w: SCSI-SEL */ + #define CATN 0x08 /* r/w: SCSI-ATN */ + #define CMSG 0x04 /* r/w: SCSI-MSG */ + #define CC_D 0x02 /* r/w: SCSI-C_D */ + #define CI_O 0x01 /* r/w: SCSI-I_O */ + +#define SSID 0x0a + +#define SBCL 0x0b + +#define DSTAT 0x0c + #define DFE 0x80 /* sta: dma fifo empty */ + #define MDPE 0x40 /* int: master data parity error */ + #define BF 0x20 /* int: script: bus fault */ + #define ABRT 0x10 /* int: script: command aborted */ + #define SSI 0x08 /* int: script: single step */ + #define SIR 0x04 /* int: script: interrupt instruct. */ + #define IID 0x01 /* int: script: illegal instruct. */ + +#define SSTAT0 0x0d + #define ILF 0x80 /* sta: data in SIDL register lsb */ + #define ORF 0x40 /* sta: data in SODR register lsb */ + #define OLF 0x20 /* sta: data in SODL register lsb */ + #define AIP 0x10 /* sta: arbitration in progress */ + #define LOA 0x08 /* sta: arbitration lost */ + #define WOA 0x04 /* sta: arbitration won */ + #define IRST 0x02 /* sta: scsi reset signal */ + #define SDP 0x01 /* sta: scsi parity signal */ + +#define SSTAT1 0x0e + #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ + +#define SSTAT2 0x0f + #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ + #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ + #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ + #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ + #define LDSC 0x02 /* sta: disconnect & reconnect */ + +#define DSA 0x10 /* --> Base page */ +#define DSA1 0x11 +#define DSA2 0x12 +#define DSA3 0x13 + +#define ISTAT 0x14 /* --> Main Command and status */ + #define CABRT 0x80 /* cmd: abort current operation */ + #define SRST 0x40 /* mod: reset chip */ + #define SIGP 0x20 /* r/w: message from host to ncr */ + #define SEM 0x10 /* r/w: message between host + ncr */ + #define CON 0x08 /* sta: connected to scsi */ + #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ + #define SIP 0x02 /* sta: scsi-interrupt */ + #define DIP 0x01 /* sta: host/script interrupt */ + + +#define CTEST0 0x18 +#define CTEST1 0x19 +#define CTEST2 0x1a + #define CSIGP 0x40 + /* bits 0-2,7 rsvd for C1010 */ + +#define CTEST3 0x1b + #define FLF 0x08 /* cmd: flush dma fifo */ + #define CLF 0x04 /* cmd: clear dma fifo */ + #define FM 0x02 /* mod: fetch pin mode */ + #define WRIE 0x01 /* mod: write and invalidate enable */ + /* bits 4-7 rsvd for C1010 */ + +#define DFIFO 0x20 +#define CTEST4 0x21 + #define BDIS 0x80 /* mod: burst disable */ + #define MPEE 0x08 /* mod: master parity error enable */ + +#define CTEST5 0x22 + #define DFS 0x20 /* mod: dma fifo size */ + /* bits 0-1, 3-7 rsvd for C1010 */ +#define CTEST6 0x23 + +#define DBC 0x24 /* ### Byte count and command */ +#define DNAD 0x28 /* ### Next command register */ +#define DSP 0x2c /* --> Script Pointer */ +#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ + +#define SCRATCHA 0x34 /* Temporary register a */ +#define SCRATCHA1 0x35 +#define SCRATCHA2 0x36 +#define SCRATCHA3 0x37 + +#define DMODE 0x38 + #define BL_2 0x80 /* mod: burst length shift value +2 */ + #define BL_1 0x40 /* mod: burst length shift value +1 */ + #define ERL 0x08 /* mod: enable read line */ + #define ERMP 0x04 /* mod: enable read multiple */ + #define BOF 0x02 /* mod: burst op code fetch */ + #define MAN 0x01 /* mod: manual start */ + +#define DIEN 0x39 +#define SBR 0x3a + +#define DCNTL 0x3b /* --> Script execution control */ + #define CLSE 0x80 /* mod: cache line size enable */ + #define PFF 0x40 /* cmd: pre-fetch flush */ + #define PFEN 0x20 /* mod: pre-fetch enable */ + #define SSM 0x10 /* mod: single step mode */ + #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ + #define STD 0x04 /* cmd: start dma mode */ + #define IRQD 0x02 /* mod: irq disable */ + #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ + /* bits 0-1 rsvd for C1010 */ + +#define ADDER 0x3c + +#define SIEN 0x40 /* -->: interrupt enable */ +#define SIST 0x42 /* <--: interrupt status */ + #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ + #define STO 0x0400/* sta: timeout (select) */ + #define GEN 0x0200/* sta: timeout (general) */ + #define HTH 0x0100/* sta: timeout (handshake) */ + #define MA 0x80 /* sta: phase mismatch */ + #define CMP 0x40 /* sta: arbitration complete */ + #define SEL 0x20 /* sta: selected by another device */ + #define RSL 0x10 /* sta: reselected by another device*/ + #define SGE 0x08 /* sta: gross error (over/underflow)*/ + #define UDC 0x04 /* sta: unexpected disconnect */ + #define RST 0x02 /* sta: scsi bus reset detected */ + #define PAR 0x01 /* sta: scsi parity error */ + +#define SLPAR 0x44 +#define SWIDE 0x45 +#define MACNTL 0x46 +#define GPCNTL 0x47 +#define STIME0 0x48 /* cmd: timeout for select&handshake*/ +#define STIME1 0x49 /* cmd: timeout user defined */ +#define RESPID 0x4a /* sta: Reselect-IDs */ + +#define STEST0 0x4c + +#define STEST1 0x4d + #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ + #define DBLEN 0x08 /* clock doubler running */ + #define DBLSEL 0x04 /* clock doubler selected */ + + +#define STEST2 0x4e + #define ROF 0x40 /* reset scsi offset (after gross error!) */ + #define EXT 0x02 /* extended filtering */ + +#define STEST3 0x4f + #define TE 0x80 /* c: tolerAnt enable */ + #define HSC 0x20 /* c: Halt SCSI Clock */ + #define CSF 0x02 /* c: clear scsi fifo */ + +#define SIDL 0x50 /* Lowlevel: latched from scsi data */ +#define STEST4 0x52 + #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ + #define SMODE_HVD 0x40 /* High Voltage Differential */ + #define SMODE_SE 0x80 /* Single Ended */ + #define SMODE_LVD 0xc0 /* Low Voltage Differential */ + #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ + /* bits 0-5 rsvd for C1010 */ + +#define SODL 0x54 /* Lowlevel: data out to scsi data */ + +#define SBDL 0x58 /* Lowlevel: data from scsi data */ + + + + +/*----------------------------------------------------------- +** +** Utility macros for the script. +** +**----------------------------------------------------------- +*/ + +#define REG(r) (r) + +/*----------------------------------------------------------- +** +** SCSI phases +** +** DT phases illegal for ncr driver. +** +**----------------------------------------------------------- +*/ + +#define SCR_DATA_OUT 0x00000000 +#define SCR_DATA_IN 0x01000000 +#define SCR_COMMAND 0x02000000 +#define SCR_STATUS 0x03000000 +#define SCR_DT_DATA_OUT 0x04000000 +#define SCR_DT_DATA_IN 0x05000000 +#define SCR_MSG_OUT 0x06000000 +#define SCR_MSG_IN 0x07000000 + +#define SCR_ILG_OUT 0x04000000 +#define SCR_ILG_IN 0x05000000 + +/*----------------------------------------------------------- +** +** Data transfer via SCSI. +** +**----------------------------------------------------------- +** +** MOVE_ABS (LEN) +** <> +** +** MOVE_IND (LEN) +** <> +** +** MOVE_TBL +** <> +** +**----------------------------------------------------------- +*/ + +#define OPC_MOVE 0x08000000 + +#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) +#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) +#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) + +#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) +#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) +#define SCR_CHMOV_TBL (0x10000000) + + +/*----------------------------------------------------------- +** +** Selection +** +**----------------------------------------------------------- +** +** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] +** <> +** +** SEL_TBL | << dnad_offset>> [ | REL_JMP] +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_SEL_ABS 0x40000000 +#define SCR_SEL_ABS_ATN 0x41000000 +#define SCR_SEL_TBL 0x42000000 +#define SCR_SEL_TBL_ATN 0x43000000 + + +#define SCR_JMP_REL 0x04000000 +#define SCR_ID(id) (((unsigned long)(id)) << 16) + +/*----------------------------------------------------------- +** +** Waiting for Disconnect or Reselect +** +**----------------------------------------------------------- +** +** WAIT_DISC +** dummy: <> +** +** WAIT_RESEL +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_WAIT_DISC 0x48000000 +#define SCR_WAIT_RESEL 0x50000000 + +/*----------------------------------------------------------- +** +** Bit Set / Reset +** +**----------------------------------------------------------- +** +** SET (flags {|.. }) +** +** CLR (flags {|.. }) +** +**----------------------------------------------------------- +*/ + +#define SCR_SET(f) (0x58000000 | (f)) +#define SCR_CLR(f) (0x60000000 | (f)) + +#define SCR_CARRY 0x00000400 +#define SCR_TRG 0x00000200 +#define SCR_ACK 0x00000040 +#define SCR_ATN 0x00000008 + + + + +/*----------------------------------------------------------- +** +** Memory to memory move +** +**----------------------------------------------------------- +** +** COPY (bytecount) +** << source_address >> +** << destination_address >> +** +** SCR_COPY sets the NO FLUSH option by default. +** SCR_COPY_F does not set this option. +** +** For chips which do not support this option, +** ncr_copy_and_bind() will remove this bit. +**----------------------------------------------------------- +*/ + +#define SCR_NO_FLUSH 0x01000000 + +#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) +#define SCR_COPY_F(n) (0xc0000000 | (n)) + +/*----------------------------------------------------------- +** +** Register move and binary operations +** +**----------------------------------------------------------- +** +** SFBR_REG (reg, op, data) reg = SFBR op data +** << 0 >> +** +** REG_SFBR (reg, op, data) SFBR = reg op data +** << 0 >> +** +** REG_REG (reg, op, data) reg = reg op data +** << 0 >> +** +**----------------------------------------------------------- +** On 810A, 860, 825A, 875, 895 and 896 chips the content +** of SFBR register can be used as data (SCR_SFBR_DATA). +** The 896 has additionnal IO registers starting at +** offset 0x80. Bit 7 of register offset is stored in +** bit 7 of the SCRIPTS instruction first DWORD. +**----------------------------------------------------------- +*/ + +#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ + +#define SCR_SFBR_REG(reg,op,data) \ + (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + +#define SCR_REG_SFBR(reg,op,data) \ + (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + +#define SCR_REG_REG(reg,op,data) \ + (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + + +#define SCR_LOAD 0x00000000 +#define SCR_SHL 0x01000000 +#define SCR_OR 0x02000000 +#define SCR_XOR 0x03000000 +#define SCR_AND 0x04000000 +#define SCR_SHR 0x05000000 +#define SCR_ADD 0x06000000 +#define SCR_ADDC 0x07000000 + +#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ + +/*----------------------------------------------------------- +** +** FROM_REG (reg) SFBR = reg +** << 0 >> +** +** TO_REG (reg) reg = SFBR +** << 0 >> +** +** LOAD_REG (reg, data) reg = +** << 0 >> +** +** LOAD_SFBR(data) SFBR = +** << 0 >> +** +**----------------------------------------------------------- +*/ + +#define SCR_FROM_REG(reg) \ + SCR_REG_SFBR(reg,SCR_OR,0) + +#define SCR_TO_REG(reg) \ + SCR_SFBR_REG(reg,SCR_OR,0) + +#define SCR_LOAD_REG(reg,data) \ + SCR_REG_REG(reg,SCR_LOAD,data) + +#define SCR_LOAD_SFBR(data) \ + (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) + +/*----------------------------------------------------------- +** +** LOAD from memory to register. +** STORE from register to memory. +** +** Only supported by 810A, 860, 825A, 875, 895 and 896. +** +**----------------------------------------------------------- +** +** LOAD_ABS (LEN) +** <> +** +** LOAD_REL (LEN) (DSA relative) +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) +#define SCR_NO_FLUSH2 0x02000000 +#define SCR_DSA_REL2 0x10000000 + +#define SCR_LOAD_R(reg, how, n) \ + (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + +#define SCR_STORE_R(reg, how, n) \ + (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + +#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) +#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) +#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) +#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) + +#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) +#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) +#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) +#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) + + +/*----------------------------------------------------------- +** +** Waiting for Disconnect or Reselect +** +**----------------------------------------------------------- +** +** JUMP [ | IFTRUE/IFFALSE ( ... ) ] +** <
> +** +** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** CALL [ | IFTRUE/IFFALSE ( ... ) ] +** <
> +** +** CALLR [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** RETURN [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** INT [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** Conditions: +** WHEN (phase) +** IF (phase) +** CARRYSET +** DATA (data, mask) +** +**----------------------------------------------------------- +*/ + +#define SCR_NO_OP 0x80000000 +#define SCR_JUMP 0x80080000 +#define SCR_JUMP64 0x80480000 +#define SCR_JUMPR 0x80880000 +#define SCR_CALL 0x88080000 +#define SCR_CALLR 0x88880000 +#define SCR_RETURN 0x90080000 +#define SCR_INT 0x98080000 +#define SCR_INT_FLY 0x98180000 + +#define IFFALSE(arg) (0x00080000 | (arg)) +#define IFTRUE(arg) (0x00000000 | (arg)) + +#define WHEN(phase) (0x00030000 | (phase)) +#define IF(phase) (0x00020000 | (phase)) + +#define DATA(D) (0x00040000 | ((D) & 0xff)) +#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) + +#define CARRYSET (0x00200000) + + + +#define SIR_COMPLETE 0x10000000 +/* script errors */ +#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 +#define SIR_CMD_OUT_ILL_PH 0x00000002 +#define SIR_STATUS_ILL_PH 0x00000003 +#define SIR_MSG_RECEIVED 0x00000004 +#define SIR_DATA_IN_ERR 0x00000005 +#define SIR_DATA_OUT_ERR 0x00000006 +#define SIR_SCRIPT_ERROR 0x00000007 +#define SIR_MSG_OUT_NO_CMD 0x00000008 +#define SIR_MSG_OVER7 0x00000009 +/* Fly interrupt */ +#define INT_ON_FY 0x00000080 + +/* Hardware errors are defined in scsi.h */ + +#define SCSI_IDENTIFY 0xC0 + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif diff --git a/common/board.c b/common/board.c index cb1dfea..d351a20 100644 --- a/common/board.c +++ b/common/board.c @@ -610,7 +610,7 @@ void board_init_r (bd_t *bd, ulong dest_addr) */ s = getenv ("flashchecksum"); if (s && (*s == 'y')) { - printf (" CRC: %08X", + printf (" CRC: %08lX", crc32 ( 0, (const unsigned char *)CFG_FLASH_BASE, flash_size) diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index b0b3f96..7d349e8 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -41,7 +41,7 @@ #include #endif - +extern int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); #undef SCSI_DEBUG diff --git a/common/hush.c b/common/hush.c index 026b39c..d90749f 100644 --- a/common/hush.c +++ b/common/hush.c @@ -131,6 +131,8 @@ #ifndef __PPCBOOT__ #define FLAG_EXIT_FROM_LOOP 1 #define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >= 2nd pass */ + #endif #ifdef __PPCBOOT__ @@ -1605,12 +1607,7 @@ static int run_pipe_real(struct pipe *pi) char * str = NULL; str = make_string((child->argv + i)); - if ((child->type & FLAG_PARSE_SEMICOLON)) { - parse_string_outer(str, FLAG_EXIT_FROM_LOOP | - FLAG_PARSE_SEMICOLON); - } else { - parse_string_outer(str, FLAG_EXIT_FROM_LOOP); - } + parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); free(str); return last_return_code; } @@ -3067,7 +3064,7 @@ int parse_stream_outer(struct in_str *inp, int flag) ctx.type = flag; initialize_context(&ctx); update_ifs_map(); - if (!(flag & FLAG_PARSE_SEMICOLON)) mapset(";$&|", 0); + if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset(";$&|", 0); inp->promptmode=1; rcode = parse_stream(&temp, &ctx, inp, '\n'); #ifdef __PPCBOOT__ @@ -3282,7 +3279,7 @@ int hush_main(int argc, char **argv) { global_argv = argv+optind; global_argc = argc-optind; - opt = parse_string_outer(optarg, 0); + opt = parse_string_outer(optarg, FLAG_PARSE_SEMICOLON); goto final_return; } break; diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index f648910..14115f0 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -41,7 +41,25 @@ cpu_init_f (void) /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ #if defined(CONFIG_MUSENKI) - CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); /* enable on-chip PCI arbitration */ +/* Why is this here, you ask? Try, just try setting 0x8000 + * in PCIACR with CONFIG_WRITE_HALFWORD() + * this one was a stumper, and we are annoyed + */ + +#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ + __asm__ __volatile__( \ + " \ + stw %2,0(%0)\n \ + sync\n \ + sth %3,2(%1)\n \ + sync\n \ + " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ + "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ + ); + + M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); #endif CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ diff --git a/include/405gp_pci.h b/include/405gp_pci.h index 0f81ce0..bf31178 100644 --- a/include/405gp_pci.h +++ b/include/405gp_pci.h @@ -1,237 +1,237 @@ -#ifndef _405GP_PCI_H -#define _405GP_PCI_H - -typedef struct pciHeaderDevice - { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - int base2; /* base address 2 */ - int base3; /* base address 3 */ - int base4; /* base address 4 */ - int base5; /* base address 5 */ - int cis; /* cardBus CIS pointer */ - short subVendorId; /* sub system vendor ID */ - short subSystemId; /* sub system ID */ - int romBase; /* expansion ROM base address */ - int reserved0; /* reserved */ - int reserved1; /* reserved */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - char minGrant; /* min Grant */ - char maxLatency; /* max Latency */ - } PCI_HEADER_DEVICE; - -typedef struct pciHeaderBridge - { - short vendorId; /* vendor ID */ - short deviceId; /* device ID */ - short command; /* command register */ - short status; /* status register */ - char revisionId; /* revision ID */ - char classCode; /* class code */ - char subClass; /* sub class code */ - char progIf; /* programming interface */ - char cacheLine; /* cache line */ - char latency; /* latency time */ - char headerType; /* header type */ - char bist; /* BIST */ - int base0; /* base address 0 */ - int base1; /* base address 1 */ - char priBus; /* primary bus number */ - char secBus; /* secondary bus number */ - char subBus; /* subordinate bus number */ - char secLatency; /* secondary latency timer */ - char ioBase; /* IO base */ - char ioLimit; /* IO limit */ - short secStatus; /* secondary status */ - short memBase; /* memory base */ - short memLimit; /* memory limit */ - short preBase; /* prefetchable memory base */ - short preLimit; /* prefetchable memory limit */ - int preBaseUpper; /* prefetchable memory base upper 32 bits */ - int preLimitUpper; /* prefetchable memory base upper 32 bits */ - short ioBaseUpper; /* IO base upper 16 bits */ - short ioLimitUpper; /* IO limit upper 16 bits */ - int reserved; /* reserved */ - int romBase; /* expansion ROM base address */ - char intLine; /* interrupt line */ - char intPin; /* interrupt pin */ - short control; /* bridge control */ - } PCI_HEADER_BRIDGE; - -/*----------------------------------------------------------------------------+ -| 405GP PCI core memory map defines. -+----------------------------------------------------------------------------*/ -#define MIN_PCI_MEMADDR1 0x80000000 -#define MIN_PCI_MEMADDR2 0x00000000 -#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ -#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ -#define MAX_PCI_DEVICES 32 - -/*----------------------------------------------------------------------------+ -| Defines for the 405GP PCI Config address and data registers followed by -| defines for the standard PCI device configuration header. -+----------------------------------------------------------------------------*/ -#define PCICFGADR 0xEEC00000 -#define PCICFGDATA 0xEEC00004 - -#define PCIVENDORID 0x00 -#define PCIDEVICEID 0x02 -#define PCICMD 0x04 - #define SERR_EN 0x0100 - #define BM_EN 0x0004 - #define MEM_EN 0x0002 - #define IO_EN 0x0001 -#define PCISTATUS 0x06 - #define CAPABLE_66MHZ 0x0020 -#define PCIREVID 0x08 -#define PCICLASSPI 0x09 -#define PCICLASSCODE 0x0A -#define PCICACHELINE 0x0C -#define PCILATENCYTIM 0x0D -#define PCIHEADERTYPE 0x0E -#define PCIBIST 0x0F -#define PCIBASEADDR0 0x10 -#define PCIBASEADDR1 0x14 -#define PCIBASEADDR2 0x18 -#define PCISSVENDORID 0x2C -#define PCISSDEVICEID 0x2E -#define PCIINTLINE 0x3C -#define PCIINTPIN 0x3D -#define PCIMINGRANT 0x3E -#define PCIMAXLATENCY 0x3F - -#define PCIBUSNUM 0x40 /* 405GP specific parameters */ -#define PCISUBBUSNUM 0x41 -#define PCIDISCOUNT 0x42 -#define PCIBRDGOPT1 0x4A -#define PCIBRDGOPT2 0x60 - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Master local configuration regs. -+----------------------------------------------------------------------------*/ -#define PMM0LA 0xEF400000 -#define PMM0MA 0xEF400004 -#define PMM0PCILA 0xEF400008 -#define PMM0PCIHA 0xEF40000C -#define PMM1LA 0xEF400010 -#define PMM1MA 0xEF400014 -#define PMM1PCILA 0xEF400018 -#define PMM1PCIHA 0xEF40001C -#define PMM2LA 0xEF400020 -#define PMM2MA 0xEF400024 -#define PMM2PCILA 0xEF400028 -#define PMM2PCIHA 0xEF40002C - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Target local configuration regs. -+----------------------------------------------------------------------------*/ -#define PTM1MS 0xEF400030 -#define PTM1LA 0xEF400034 -#define PTM2MS 0xEF400038 -#define PTM2LA 0xEF40003C - -/*-----------------------------------------------------------------------------+ -| PCI-PCI bridge header -+-----------------------------------------------------------------------------*/ -#define PCIPCI_PRIMARYBUS 0x18 -#define PCIPCI_SECONDARYBUS 0x19 -#define PCIPCI_SUBORDINATEBUS 0x1A -#define PCIPCI_SECONDARYLATENCY 0x1B -#define PCIPCI_IOBASE 0x1C -#define PCIPCI_IOLIMIT 0x1D -#define PCIPCI_SECONDARYSTATUS 0x1E -#define PCIPCI_MEMBASE 0x20 -#define PCIPCI_MEMLIMIT 0x22 -#define PCIPCI_PREFETCHMEMBASE 0x24 -#define PCIPCI_PREFETCHMEMLIMIT 0x26 -#define PCIPCI_IOBASEUPPER16 0x30 -#define PCIPCI_IOLIMITUPPER16 0x32 - -#define PCIDEVID_405GP 0x0 - -/* Standard device configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDER_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - - -/* PCI-to-PCI bridge configuration register offsets */ -/* Note that only modulo-4 addresses are written to the address register */ - -#define PCI_CFG_PRIMARY_BUS 0x18 -#define PCI_CFG_SECONDARY_BUS 0x19 -#define PCI_CFG_SUBORDINATE_BUS 0x1a -#define PCI_CFG_SEC_LATENCY 0x1b -#define PCI_CFG_IO_BASE 0x1c -#define PCI_CFG_IO_LIMIT 0x1d -#define PCI_CFG_SEC_STATUS 0x1e -#define PCI_CFG_MEM_BASE 0x20 -#define PCI_CFG_MEM_LIMIT 0x22 -#define PCI_CFG_PRE_MEM_BASE 0x24 -#define PCI_CFG_PRE_MEM_LIMIT 0x26 -#define PCI_CFG_PRE_MEM_BASE_U 0x28 -#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c -#define PCI_CFG_IO_BASE_U 0x30 -#define PCI_CFG_IO_LIMIT_U 0x32 -#define PCI_CFG_ROM_BASE 0x38 -#define PCI_CFG_BRG_INT_LINE 0x3c -#define PCI_CFG_BRG_INT_PIN 0x3d -#define PCI_CFG_BRIDGE_CONTROL 0x3e - - - -unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); -int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); -void PCI_Scan(int BusNum); -void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); -void PCI_Config_Bridge(int BusDevFunc); -void PCI_Dump_Device(int BusDevFunc); -int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); -void pciHeaderShow(int BusDevFunc); -void pciDheaderPrint(PCI_HEADER_DEVICE * pD); -void pciBheaderPrint(PCI_HEADER_BRIDGE * pB); - -#endif +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +typedef struct pciHeaderDevice + { + short vendorId; /* vendor ID */ + short deviceId; /* device ID */ + short command; /* command register */ + short status; /* status register */ + char revisionId; /* revision ID */ + char classCode; /* class code */ + char subClass; /* sub class code */ + char progIf; /* programming interface */ + char cacheLine; /* cache line */ + char latency; /* latency time */ + char headerType; /* header type */ + char bist; /* BIST */ + int base0; /* base address 0 */ + int base1; /* base address 1 */ + int base2; /* base address 2 */ + int base3; /* base address 3 */ + int base4; /* base address 4 */ + int base5; /* base address 5 */ + int cis; /* cardBus CIS pointer */ + short subVendorId; /* sub system vendor ID */ + short subSystemId; /* sub system ID */ + int romBase; /* expansion ROM base address */ + int reserved0; /* reserved */ + int reserved1; /* reserved */ + char intLine; /* interrupt line */ + char intPin; /* interrupt pin */ + char minGrant; /* min Grant */ + char maxLatency; /* max Latency */ + } PCI_HEADER_DEVICE; + +typedef struct pciHeaderBridge + { + short vendorId; /* vendor ID */ + short deviceId; /* device ID */ + short command; /* command register */ + short status; /* status register */ + char revisionId; /* revision ID */ + char classCode; /* class code */ + char subClass; /* sub class code */ + char progIf; /* programming interface */ + char cacheLine; /* cache line */ + char latency; /* latency time */ + char headerType; /* header type */ + char bist; /* BIST */ + int base0; /* base address 0 */ + int base1; /* base address 1 */ + char priBus; /* primary bus number */ + char secBus; /* secondary bus number */ + char subBus; /* subordinate bus number */ + char secLatency; /* secondary latency timer */ + char ioBase; /* IO base */ + char ioLimit; /* IO limit */ + short secStatus; /* secondary status */ + short memBase; /* memory base */ + short memLimit; /* memory limit */ + short preBase; /* prefetchable memory base */ + short preLimit; /* prefetchable memory limit */ + int preBaseUpper; /* prefetchable memory base upper 32 bits */ + int preLimitUpper; /* prefetchable memory base upper 32 bits */ + short ioBaseUpper; /* IO base upper 16 bits */ + short ioLimitUpper; /* IO limit upper 16 bits */ + int reserved; /* reserved */ + int romBase; /* expansion ROM base address */ + char intLine; /* interrupt line */ + char intPin; /* interrupt pin */ + short control; /* bridge control */ + } PCI_HEADER_BRIDGE; + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIVENDORID 0x00 +#define PCIDEVICEID 0x02 +#define PCICMD 0x04 + #define SERR_EN 0x0100 + #define BM_EN 0x0004 + #define MEM_EN 0x0002 + #define IO_EN 0x0001 +#define PCISTATUS 0x06 + #define CAPABLE_66MHZ 0x0020 +#define PCIREVID 0x08 +#define PCICLASSPI 0x09 +#define PCICLASSCODE 0x0A +#define PCICACHELINE 0x0C +#define PCILATENCYTIM 0x0D +#define PCIHEADERTYPE 0x0E +#define PCIBIST 0x0F +#define PCIBASEADDR0 0x10 +#define PCIBASEADDR1 0x14 +#define PCIBASEADDR2 0x18 +#define PCISSVENDORID 0x2C +#define PCISSDEVICEID 0x2E +#define PCIINTLINE 0x3C +#define PCIINTPIN 0x3D +#define PCIMINGRANT 0x3E +#define PCIMAXLATENCY 0x3F + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +/*-----------------------------------------------------------------------------+ +| PCI-PCI bridge header ++-----------------------------------------------------------------------------*/ +#define PCIPCI_PRIMARYBUS 0x18 +#define PCIPCI_SECONDARYBUS 0x19 +#define PCIPCI_SUBORDINATEBUS 0x1A +#define PCIPCI_SECONDARYLATENCY 0x1B +#define PCIPCI_IOBASE 0x1C +#define PCIPCI_IOLIMIT 0x1D +#define PCIPCI_SECONDARYSTATUS 0x1E +#define PCIPCI_MEMBASE 0x20 +#define PCIPCI_MEMLIMIT 0x22 +#define PCIPCI_PREFETCHMEMBASE 0x24 +#define PCIPCI_PREFETCHMEMLIMIT 0x26 +#define PCIPCI_IOBASEUPPER16 0x30 +#define PCIPCI_IOLIMITUPPER16 0x32 + +#define PCIDEVID_405GP 0x0 + +/* Standard device configuration register offsets */ +/* Note that only modulo-4 addresses are written to the address register */ + +#define PCI_CFG_VENDOR_ID 0x00 +#define PCI_CFG_DEVICE_ID 0x02 +#define PCI_CFG_COMMAND 0x04 +#define PCI_CFG_STATUS 0x06 +#define PCI_CFG_REVISION 0x08 +#define PCI_CFG_PROGRAMMING_IF 0x09 +#define PCI_CFG_SUBCLASS 0x0a +#define PCI_CFG_CLASS 0x0b +#define PCI_CFG_CACHE_LINE_SIZE 0x0c +#define PCI_CFG_LATENCY_TIMER 0x0d +#define PCI_CFG_HEADER_TYPE 0x0e +#define PCI_CFG_BIST 0x0f +#define PCI_CFG_BASE_ADDRESS_0 0x10 +#define PCI_CFG_BASE_ADDRESS_1 0x14 +#define PCI_CFG_BASE_ADDRESS_2 0x18 +#define PCI_CFG_BASE_ADDRESS_3 0x1c +#define PCI_CFG_BASE_ADDRESS_4 0x20 +#define PCI_CFG_BASE_ADDRESS_5 0x24 +#define PCI_CFG_CIS 0x28 +#define PCI_CFG_SUB_VENDER_ID 0x2c +#define PCI_CFG_SUB_SYSTEM_ID 0x2e +#define PCI_CFG_EXPANSION_ROM 0x30 +#define PCI_CFG_RESERVED_0 0x34 +#define PCI_CFG_RESERVED_1 0x38 +#define PCI_CFG_DEV_INT_LINE 0x3c +#define PCI_CFG_DEV_INT_PIN 0x3d +#define PCI_CFG_MIN_GRANT 0x3e +#define PCI_CFG_MAX_LATENCY 0x3f +#define PCI_CFG_SPECIAL_USE 0x41 +#define PCI_CFG_MODE 0x43 + + +/* PCI-to-PCI bridge configuration register offsets */ +/* Note that only modulo-4 addresses are written to the address register */ + +#define PCI_CFG_PRIMARY_BUS 0x18 +#define PCI_CFG_SECONDARY_BUS 0x19 +#define PCI_CFG_SUBORDINATE_BUS 0x1a +#define PCI_CFG_SEC_LATENCY 0x1b +#define PCI_CFG_IO_BASE 0x1c +#define PCI_CFG_IO_LIMIT 0x1d +#define PCI_CFG_SEC_STATUS 0x1e +#define PCI_CFG_MEM_BASE 0x20 +#define PCI_CFG_MEM_LIMIT 0x22 +#define PCI_CFG_PRE_MEM_BASE 0x24 +#define PCI_CFG_PRE_MEM_LIMIT 0x26 +#define PCI_CFG_PRE_MEM_BASE_U 0x28 +#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c +#define PCI_CFG_IO_BASE_U 0x30 +#define PCI_CFG_IO_LIMIT_U 0x32 +#define PCI_CFG_ROM_BASE 0x38 +#define PCI_CFG_BRG_INT_LINE 0x3c +#define PCI_CFG_BRG_INT_PIN 0x3d +#define PCI_CFG_BRIDGE_CONTROL 0x3e + + + +unsigned int PCI_Read_CFG_Reg(int BusDevFunc, int Reg, int Width); +int PCI_Write_CFG_Reg(int BusDevFunc, int Reg, unsigned int Value, int Width); +void PCI_Scan(int BusNum); +void PCI_Config_Device(int BusDevFunc, int NumBaseAddr); +void PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr); +void PCI_Config_Bridge(int BusDevFunc); +void PCI_Dump_Device(int BusDevFunc); +int PCI_Find_Device(unsigned short VendorID, unsigned short DeviceID); +void pciHeaderShow(int BusDevFunc); +void pciDheaderPrint(PCI_HEADER_DEVICE * pD); +void pciBheaderPrint(PCI_HEADER_BRIDGE * pB); + +#endif diff --git a/include/config_PCIPPC6.h b/include/config_PCIPPC6.h new file mode 100644 index 0000000..bbcbacb --- /dev/null +++ b/include/config_PCIPPC6.h @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the PCIPPC-6 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ + +#define CONFIG_BOARD_PRE_INIT 1 +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ + +#define CONFIG_PREBOOT "" +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_DOC | \ + CFG_CMD_DATE | \ + CFG_CMD_SCSI ) + + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 64 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_MAX_SIZE 0x00100000 +/* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ + CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* Size in bytes reserved for initial data + */ +#define CFG_INIT_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x8000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +#define CFG_INIT_RAM_LOCK + +/* + * Temporary buffer for serial data until the real serial driver + * is initialised (memtest will destroy this buffer) + */ +#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR +#define CFG_SCONSOLE_SIZE 0x0002000 + +/* SDRAM 0 - 256MB + */ +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (CFG_SDRAM_BASE | \ + BATU_BL_256M | BATU_VS | BATU_VP) +/* SDRAM 1 - 256MB + */ +#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ + BATU_BL_256M | BATU_VS | BATU_VP) + +/* Init RAM in the CPU DCache (no backing memory) + */ +#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ + BATU_BL_128K | BATU_VS | BATU_VP) + +/* I/O and PCI memory at 0xf0000000 + */ +#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT0L CFG_DBAT0L +#define CFG_IBAT0U CFG_DBAT0U +#define CFG_IBAT1L CFG_DBAT1L +#define CFG_IBAT1U CFG_DBAT1U +#define CFG_IBAT2L CFG_DBAT2L +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT3L CFG_DBAT3L +#define CFG_IBAT3U CFG_DBAT3U + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the PCIPPC2 user's manual. + */ +#define CFG_HZ 1000 +#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CFG_CPU_CLK 300000000 +#define CFG_BUS_CLK 100000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +/* + * Note: environment is not EMBEDDED in the ppcboot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2 cache + */ +#undef CFG_L2 +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#undef CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + RTC m48t59 +*/ +#define CONFIG_RTC_MK48T59 + +#define CONFIG_WATCHDOG + + + +#define CONFIG_SCSI_SYM53C8XX +#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ +#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ +#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ +#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ +#define CFG_SCSI_SPIN_UP_TIME 2 +#define CFG_SCSI_SCAN_BUS_REVERSE 0 +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION + + + +#endif /* __CONFIG_H */ diff --git a/include/hush.h b/include/hush.h index e3a08f0..6e7fc0f 100644 --- a/include/hush.h +++ b/include/hush.h @@ -26,7 +26,7 @@ #define FLAG_EXIT_FROM_LOOP 1 #define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ -#define FLAG_NOT_PARSE_SEMICOLON (1 << 2) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ extern int ppcboot_hush_start(bd_t *bd); extern int parse_string_outer(char *s, int flag); diff --git a/net/net.c b/net/net.c index a20ee81..48c76fc 100644 --- a/net/net.c +++ b/net/net.c @@ -262,18 +262,19 @@ restart: /**********************************************************************/ +#ifndef CONFIG_NET_MULTI static void startAgainTimeout(void) { NetState = NETLOOP_RESTART; } - static void startAgainHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) { /* Totally ignore the packet */ } +#endif void