From: Alexander Duyck Date: Tue, 3 Nov 2015 01:09:35 +0000 (-0800) Subject: ixgbe: Fix SR-IOV VLAN pool configuration X-Git-Tag: v4.1.12-92~126^2~182 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=5b547af61d3d81daa77235ae8e4b92ddfa50563f;p=users%2Fjedix%2Flinux-maple.git ixgbe: Fix SR-IOV VLAN pool configuration Orabug: 23177316 The code for checking the PF bit in ixgbe_set_vf_vlan_msg was using the wrong offset and as a result it was pulling the VLAN off of the PF even if there were VFs numbered greater than 40 that still had the VLAN enabled. Signed-off-by: Alexander Duyck Tested-by: Phil Schmitt Signed-off-by: Jeff Kirsher (cherry picked from commit 8e8e9a0b7df0194e95bb1d657f9edbdc6363f082) Signed-off-by: Brian Maly --- diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 5f663ed8d7a54..c98325f6bf86f 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -884,10 +884,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter, bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); bits &= ~(1 << VMDQ_P(0)); bits |= IXGBE_READ_REG(hw, - IXGBE_VLVFB(reg_ndx * 2) + 1); + IXGBE_VLVFB(reg_ndx * 2 + 1)); } else { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB(reg_ndx * 2) + 1); + IXGBE_VLVFB(reg_ndx * 2 + 1)); bits &= ~(1 << (VMDQ_P(0) - 32)); bits |= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); }