From: KarimAllah Ahmed Date: Sat, 3 Feb 2018 14:56:23 +0000 (+0100) Subject: KVM/SVM: Allow direct access to MSR_IA32_SPEC_CTRL X-Git-Tag: v4.1.12-124.31.3~337 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=53da198cf7a918baa7ac267af1d89b71bc117ce9;p=users%2Fjedix%2Flinux-maple.git KVM/SVM: Allow direct access to MSR_IA32_SPEC_CTRL [ Based on a patch from Paolo Bonzini ] ... basically doing exactly what we do for VMX: - Passthrough SPEC_CTRL to guests (if enabled in guest CPUID) - Save and restore SPEC_CTRL around VMExit and VMEntry only if the guest actually used it. Signed-off-by: KarimAllah Ahmed Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Reviewed-by: Darren Kenny Reviewed-by: Konrad Rzeszutek Wilk Cc: Andrea Arcangeli Cc: Andi Kleen Cc: Jun Nakajima Cc: kvm@vger.kernel.org Cc: Dave Hansen Cc: Tim Chen Cc: Andy Lutomirski Cc: Asit Mallick Cc: Arjan Van De Ven Cc: Greg KH Cc: Paolo Bonzini Cc: Dan Williams Cc: Linus Torvalds Cc: Ashok Raj Link: https://lkml.kernel.org/r/1517669783-20732-1-git-send-email-karahmed@amazon.de Signed-off-by: Greg Kroah-Hartman (cherry picked from commit b2ac58f90540e39324e7a29a7ad471407ae0bf48) Orabug: 28069548 Signed-off-by: Mihai Carabas Reviewed-by: Darren Kenny Reviewed-by: Boris Ostrovsky Signed-off-by: Brian Maly Conflicts: arch/x86/kvm/svm.c Contextual and also we dropped msr_write_intercepted because we do not use it (we have other logic for IBRS usage). No changes to svm_vcpu_run() because we support IBRS and we have other code in place. Signed-off-by: Brian Maly --- diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 09f118462999..b6bf48bd74c9 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -193,7 +193,7 @@ static const struct svm_direct_access_msrs { { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, { .index = MSR_IA32_LASTINTFROMIP, .always = false }, { .index = MSR_IA32_LASTINTTOIP, .always = false }, - { .index = MSR_IA32_SPEC_CTRL, .always = true }, + { .index = MSR_IA32_SPEC_CTRL, .always = false }, { .index = MSR_IA32_PRED_CMD, .always = false }, { .index = MSR_INVALID, .always = false }, }; @@ -3176,6 +3176,11 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) msr_info->data = svm->nested.vm_cr_msr; break; case MSR_IA32_SPEC_CTRL: + if (!msr_info->host_initiated && + !guest_cpuid_has_ibrs(vcpu) && + !guest_cpuid_has_ssbd(vcpu)) + return 1; + msr_info->data = svm->spec_ctrl; break; case MSR_AMD64_VIRT_SPEC_CTRL: @@ -3301,7 +3306,32 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); break; case MSR_IA32_SPEC_CTRL: + if (!msr->host_initiated && + !guest_cpuid_has_ibrs(vcpu) && + !guest_cpuid_has_ssbd(vcpu)) + return 1; + + /* The STIBP bit doesn't fault even if it's not advertised */ + if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP)) + return 1; + svm->spec_ctrl = data; + + if (!data) + break; + + /* + * For non-nested: + * When it's written (to non-zero) for the first time, pass + * it through. + * + * For nested: + * The handling of the MSR bitmap for L2 guests is done in + * nested_svm_vmrun_msrpm. + * We update the L1 MSR bit as well since it will end up + * touching the MSR anyway now. + */ + set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1); break; case MSR_IA32_PRED_CMD: if (!msr->host_initiated &&