From: wdenk Date: Sun, 10 Mar 2002 19:04:15 +0000 (+0000) Subject: * Add configuration for MicroSys CPU86 board X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=530381727aa07bf65b4e12e13aef55c5a7a55e0b;p=users%2Frw%2Fppcboot.git * Add configuration for MicroSys CPU86 board * Patch by Erik Theisen, 9 Mar 2002: VPD patch for W7O boards --- diff --git a/CHANGELOG b/CHANGELOG index a848d3d..0263eb3 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,11 @@ Modifications for 1.1.6: ====================================================================== +* Add configuration for MicroSys CPU86 board + +* Patch by Erik Theisen, 9 Mar 2002: + VPD patch for W7O boards + * Patch by Jerry Van Baren, 08 Mar 2002: Grand Unifying I2C interface patch diff --git a/MAINTAINERS b/MAINTAINERS index 890161f..f69046c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -42,6 +42,7 @@ Wolfgang Denk CU824 MPC8240 Sandpoint8240 MPC8240 + CPU86 MPC8260 IPHASE4539 MPC8260 PM826 MPC8260 TQM8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index b196b47..fc8829d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -53,9 +53,10 @@ LIST_824x=" \ ######################################################################### LIST_8260=" \ - cogent_mpc8260 ep8260 gw8260 hymod \ - IPHASE4539 MPC8260ADS PM826 ppmc8260 \ - RPXsuper rsdproto sbc8260 TQM8260 \ + cogent_mpc8260 CPU86 ep8260 gw8260 \ + hymod IPHASE4539 MPC8260ADS PM826 \ + ppmc8260 RPXsuper rsdproto sbc8260 \ + TQM8260 \ " ######################################################################### diff --git a/Makefile b/Makefile index c8a4a4a..b91ee00 100644 --- a/Makefile +++ b/Makefile @@ -640,6 +640,15 @@ cogent_mpc8260_config: unconfig echo "CPU = mpc8260" >>config.mk ; \ echo "#include " >config.h +CPU86_config: unconfig + @echo "Configuring for $(call xtract,$@) Board..." ; \ + cd ./include ; \ + echo "ARCH = ppc" > config.mk ; \ + echo "BOARD = cpu86" >>config.mk ; \ + echo "CPU = mpc8260" >>config.mk ; + @echo "/* Automatically generated - do not edit */" >include/config.h + @echo "#include " >>include/config.h + ep8260_config: unconfig @echo "Configuring for $(@:_config=) Board..." ; \ cd ./include ; \ diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile new file mode 100644 index 0000000..35b8428 --- /dev/null +++ b/board/cpu86/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk new file mode 100644 index 0000000..6a9fab2 --- /dev/null +++ b/board/cpu86/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CPU86 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h +# for the "final" configuration, with ppcboot in flash, or the address +# in RAM where ppcboot is loaded at for debugging. +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c new file mode 100644 index 0000000..a637cb7 --- /dev/null +++ b/board/cpu86/cpu86.c @@ -0,0 +1,328 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "cpu86.h" + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard(void) +{ + printf("CPU86 (Rev %02x)\n", CPU86_REV); + return 1; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init(volatile memctl8260_t *memctl, ulong sdmr, ulong orx, + volatile uchar * base) +{ + volatile uchar c = 0xff; + ulong cnt, val; + volatile ulong * addr; + volatile uint * sdmr_ptr; + volatile uint * orx_ptr; + int i; + ulong save[32]; /* to make test non-destructive */ + ulong maxsize; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + /* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + i = 0; + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { + addr = (volatile ulong *)base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *)base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { + addr = (volatile ulong *)base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + /* Write the actual size to ORx + */ + *orx_ptr = orx | ~(cnt * sizeof(long) - 1); + return (cnt * sizeof(long)); + } + } + return (maxsize); +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + long psize; + + psize = 32 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + psize = try_init(memctl, CFG_PSDMR, CFG_OR2_PRELIM, + (uchar *) CFG_SDRAM_BASE); +#endif /* CFG_RAMBOOT */ + + icache_enable(); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe(ulong physadr); +void doc_init (void) +{ + doc_probe(CFG_DOC_BASE); +} +#endif diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h new file mode 100644 index 0000000..cf7852c --- /dev/null +++ b/board/cpu86/cpu86.h @@ -0,0 +1,27 @@ +#ifndef __BOARD_CPU86__ +#define __BOARD_CPU86__ + +#include + +#define REG8(x) (*(volatile unsigned char *)(x)) + +/* CPU86 register definitions */ +#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) + +/* Board Control Register bits */ +#define CPU86_BCR_FWPT 0x01 +#define CPU86_BCR_FWRE 0x02 + +#endif /* __BOARD_CPU86__ */ diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c new file mode 100644 index 0000000..062f46d --- /dev/null +++ b/board/cpu86/flash.c @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AM290[48]0B devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "cpu86.h" + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_char *addr, flash_info_t *info); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size, totsize; + int i; + ulong addr; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return (totsize); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id >> 16) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F080B: + printf ("AM29F080B (8 Mbit)\n"); + break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_char *addr, flash_info_t *info) +{ + short i; + uchar vendor, devid; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x90; + + udelay(1000); + + vendor = addr[0]; + devid = addr[1] & 0xff; + + /* only support AMD */ + if (vendor != 0x01) { + return 0; + } + + vendor &= 0xf; + devid &= 0xff; + + if (devid == AMD_ID_F040B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 8; + info->size = info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F080B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 16; + info->size = 4 * info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F016D) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; + info->size = 4 * info->sector_count * 0x10000; + } + else { + printf ("## Unknown Flash Type: %02x\n", devid); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_char *)(info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr, *src)) != 0) { + return (rc); + } + addr++; + src++; + cnt--; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cpu86/ppcboot.lds b/board/cpu86/ppcboot.lds new file mode 100644 index 0000000..5df4cdb --- /dev/null +++ b/board/cpu86/ppcboot.lds @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/w7o/Makefile b/board/w7o/Makefile index 7edebc2..d008f89 100644 --- a/board/w7o/Makefile +++ b/board/w7o/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o watchdog.o +OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ + watchdog.o SOBJS = init.o post1.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/w7o/config.mk b/board/w7o/config.mk index 68421e0..c73329e 100644 --- a/board/w7o/config.mk +++ b/board/w7o/config.mk @@ -28,5 +28,5 @@ #TEXT_BASE = 0xFFF80000 TEXT_BASE = 0xFFFC0000 -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD) +#PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD) diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index eac3947..82f442b 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -44,7 +44,7 @@ #define IIC_CNTL_CHT 0x04 /* STS Register Bit definition */ -#DEFIne IIC_STS_PT 0X01 +#define IIC_STS_PT 0X01 #define IIC_STS_ERR 0X04 #define IIC_STS_MDBS 0X20 diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index f2862ee..6386d42 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -55,27 +55,25 @@ /* Dump out to the screen PHY regs */ /***********************************************************/ -void miiphy_dump(unsigned char addr) +void miiphy_dump (unsigned char addr) { - unsigned long i; - unsigned short data; + unsigned long i; + unsigned short data; - for(i=0; i<0x1A; i++) - { - if(miiphy_read(addr, i, &data)) - { - printf("read error for reg %lx\n",i); - return; - } - printf("Phy reg %lx ==> %4x\n", i, data); + for (i = 0; i < 0x1A; i++) { + if (miiphy_read (addr, i, &data)) { + printf ("read error for reg %lx\n", i); + return; + } + printf ("Phy reg %lx ==> %4x\n", i, data); - /* jump to the next set of regs */ - if(i==0x07) - i=0x0f; + /* jump to the next set of regs */ + if (i == 0x07) + i = 0x0f; - } /* end for loop */ -} /* end dump */ + } /* end for loop */ +} /* end dump */ @@ -83,54 +81,54 @@ void miiphy_dump(unsigned char addr) /* read a phy reg and return the value with a rc */ /***********************************************************/ -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value) +int miiphy_read (unsigned char addr, unsigned char reg, + unsigned short *value) { - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; - - /* see if it is ready for 1000 nsec */ - i=0; - - /* see if it is ready for sec */ - while((in32(EMAC_STACR) & EMAC_STACR_OC) == 0) - { - udelay(7); - if(i > 5) - { printf("read err 1\n"); - return -1; - } - i++; - } - sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ - sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; - sta_reg = sta_reg | (addr << 5); /* Phy address */ - - out32(EMAC_STACR, sta_reg); -#if 0 /* test-only */ - printf("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; + + /* see if it is ready for 1000 nsec */ + i = 0; + + /* see if it is ready for sec */ + while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) { + printf ("read err 1\n"); + return -1; + } + i++; + } + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ + sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; + sta_reg = sta_reg | (addr << 5); /* Phy address */ + + out32 (EMAC_STACR, sta_reg); +#if 0 /* test-only */ + printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif - sta_reg = in32(EMAC_STACR); - i=0; - while(( sta_reg & EMAC_STACR_OC) == 0) - { - udelay(7); - if(i > 5) - { printf("read err 2\n"); - return -1; - } - i++; - sta_reg = in32(EMAC_STACR); - } - if ((sta_reg & EMAC_STACR_PHYE) !=0) - { printf("read err 3\n"); - printf("a2: read: EMAC_STACR=0x%0lx, i=%d\n", sta_reg, (int)i); /* test-only */ - return -1; - } - - *value = *(short *)(&sta_reg); - return 0; + sta_reg = in32 (EMAC_STACR); + i = 0; + while ((sta_reg & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) { + printf ("read err 2\n"); + return -1; + } + i++; + sta_reg = in32 (EMAC_STACR); + } + if ((sta_reg & EMAC_STACR_PHYE) != 0) { + printf ("read err 3\n"); + printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n", + sta_reg, (int) i); /* test-only */ + return -1; + } + + *value = *(short *) (&sta_reg); + return 0; } /* phy_read */ @@ -140,46 +138,45 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value) /* write a phy reg and return the value with a rc */ /***********************************************************/ -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) +int miiphy_write (unsigned char addr, unsigned char reg, + unsigned short value) { - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; - - /* see if it is ready for 1000 nsec */ - i=0; - - while((in32(EMAC_STACR) & EMAC_STACR_OC) == 0) - { - if(i>5) - return -1; - udelay(7); - i++; - } - sta_reg=0; - sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ - sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; - sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */ - memcpy(&sta_reg, &value,2); /* put in data */ - - out32(EMAC_STACR, sta_reg); - - /* wait for completion */ - i=0; - sta_reg = in32(EMAC_STACR); - while(( sta_reg & EMAC_STACR_OC) == 0) - { - udelay(7); - if(i > 5) - return -1; - i++; - sta_reg = in32(EMAC_STACR); - } - - if ((sta_reg & EMAC_STACR_PHYE) !=0) - return -1; - return 0; + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; + + /* see if it is ready for 1000 nsec */ + i = 0; + + while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) { + if (i > 5) + return -1; + udelay (7); + i++; + } + sta_reg = 0; + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ + sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; + sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ + memcpy (&sta_reg, &value, 2); /* put in data */ + + out32 (EMAC_STACR, sta_reg); + + /* wait for completion */ + i = 0; + sta_reg = in32 (EMAC_STACR); + while ((sta_reg & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) + return -1; + i++; + sta_reg = in32 (EMAC_STACR); + } + + if ((sta_reg & EMAC_STACR_PHYE) != 0) + return -1; + return 0; } /* phy_read */ -#endif /* CONFIG_405GP */ +#endif /* CONFIG_405GP */ diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h index ccf9919..a5f0d56 100644 --- a/include/cmd_bsp.h +++ b/include/cmd_bsp.h @@ -204,6 +204,21 @@ int zuma_test_dma(int cmd, int size); #endif /* CONFIG_EVB64260 */ /* ----------------------------------------------------------------------------*/ +/* -----W7O--------------------------------------------------------------------*/ +#if defined(CONFIG_W7O) + +#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ + "vpd", 3, 2, 1, do_vpd, \ + "vpd - Read Vital Product Data\n", \ + "[dev_addr]\n" \ + " - Read VPD Data from default address, or device address 'dev_addr'.\n" \ +), + +extern int do_vpd (cmd_tbl_t *, bd_t *, int, int, char *[]); + +#endif /* CONFIG_W7O */ +/* ----------------------------------------------------------------------------*/ + #else #define CMD_TBL_BSP #endif /* CFG_CMD_BSP */ diff --git a/include/config_CPU86.h b/include/config_CPU86.h new file mode 100644 index 0000000..8f09367 --- /dev/null +++ b/include/config_CPU86.h @@ -0,0 +1,630 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_CPU86 1 /* ...on a CPU86 board */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK12 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 64000000 /* in Hz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT \ + "echo; " \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "bootm" + +/*----------------------------------------------------------------------- + * I2C/EEPROM/RTC configuration + */ +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00000010) +#define I2C_TRISTATE (iop->pdir &= ~0x00000010) +#define I2C_READ ((iop->pdat & 0x00000010) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ + else iop->pdat &= ~0x00000010 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ + else iop->pdat &= ~0x00000020 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + * Miscellaneous configuration options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM | \ + CFG_CMD_DATE | CFG_CMD_DOC) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash configuration + */ + +#define CONFIG_BOOT_BOOTROM /* BTMD jumpers are set to 1-2, 3-4 */ + +#ifdef CONFIG_BOOT_BOOTROM +# define CFG_BOOTROM_BASE 0xFFF00000 +# define CFG_BOOTROM_SIZE 0x00100000 +# define CFG_BFLASH_BASE 0xFF000000 +# define CFG_BFLASH_SIZE 0x00800000 +# define CFG_FLASH_BASE CFG_BOOTROM_BASE +# define CFG_FLASH_SIZE CFG_BOOTROM_SIZE +#else +# define CFG_BOOTROM_BASE 0xFF000000 +# define CFG_BOOTROM_SIZE 0x00100000 +# define CFG_BFLASH_BASE 0xFF800000 +# define CFG_BFLASH_SIZE 0x00800000 +# define CFG_FLASH_BASE CFG_BFLASH_BASE +# define CFG_FLASH_SIZE CFG_BFLASH_SIZE +#endif + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/*----------------------------------------------------------------------- + * Other areas to be mapped + */ + +/* CS3: Dual ported SRAM */ +#define CFG_DPSRAM_BASE 0x40000000 +#define CFG_DPSRAM_SIZE 0x00020000 + +/* CS4: DiskOnChip */ +#define CFG_DOC_BASE 0xF4000000 +#define CFG_DOC_SIZE 0x00100000 + +/* CS5: FDC37C78 controller */ +#define CFG_FDC37C78_BASE 0xF1000000 +#define CFG_FDC37C78_SIZE 0x00100000 + +/* CS6: Board configuration registers */ +#define CFG_BCRS_BASE 0xF2000000 +#define CFG_BCRS_SIZE 0x00010000 + +/* CS7: VME Extended Access Range */ +#define CFG_VMEEAR_BASE 0x80000000 +#define CFG_VMEEAR_SIZE 0x01000000 + +/* CS8: VME Standard Access Range */ +#define CFG_VMESAR_BASE 0xFE000000 +#define CFG_VMESAR_SIZE 0x01000000 + +/* CS9: VME Short I/O Access Range */ +#define CFG_VMESIOAR_BASE 0xFD000000 +#define CFG_VMESIOAR_SIZE 0x01000000 + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CS10PC01) + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_DEFAULT_IMMR 0x00010000 +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#if 0 +/* environment is in Flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_BOOT_BOOTROM +# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) +# define CFG_ENV_SIZE 0x10000 +# define CFG_ENV_SECT_SIZE 0x10000 +#endif +#else +/* environment is in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ + HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ + SIUMCR_CS10PC01|SIUMCR_BCTLC10) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-18 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR 0x4000 + +/*----------------------------------------------------------------------- + * PSRT - Refresh Timer Register 10-16 + *----------------------------------------------------------------------- + */ +#define CFG_PSRT 0x0f + +/*----------------------------------------------------------------------- + * PSRT - SDRAM Mode Register 10-10 + *----------------------------------------------------------------------- + */ +#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit Boot ROM + * 1 60x GPCM 64 bit FLASH + * 2 60x SDRAM 64 bit SDRAM + * + */ + +#define CFG_MRS_OFFS 0x00000000 + +#ifdef CONFIG_BOOT_BOOTROM +/* Bank 0 - Boot ROM + */ +#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - FLASH + */ +#define CFG_BR1_PRELIM ((CFG_BFLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BFLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +#else /* CONFIG_BOOT_BOOTROM */ +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_BFLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BFLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - Boot ROM + */ +#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +#endif /* CONFIG_BOOT_BOOTROM */ + + +/* Bank 2 - 60x bus SDRAM + */ +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM ((~(CFG_SDRAM_MAX_SIZE-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) +#endif /* CFG_RAMBOOT */ + +/* Bank 3 - Dual Ported SRAM + */ +#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 4 - DiskOnChip + */ +#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 5 - FDC37C78 controller + */ +#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_8_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 6 - Board control registers + */ +#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ + ORxG_CSNT |\ + ORxG_SCY_5_CLK) + +/* Bank 7 - VME Extended Access Range + */ +#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 8 - VME Standard Access Range + */ +#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 9 - VME Short I/O Access Range + */ +#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +#endif /* __CONFIG_H */ diff --git a/include/config_ICU862.h b/include/config_ICU862.h index d719659..325af02 100644 --- a/include/config_ICU862.h +++ b/include/config_ICU862.h @@ -117,6 +117,7 @@ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ CFG_CMD_IDE | \ CFG_CMD_DATE ) diff --git a/include/config_PM826.h b/include/config_PM826.h index 319da10..db95293 100644 --- a/include/config_PM826.h +++ b/include/config_PM826.h @@ -73,8 +73,8 @@ else iop->pdat &= ~0x00000020 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_RTC_PCF8563 +#define CONFIG_RTC_PCF8563 #define CFG_I2C_RTC_ADDR 0x51 /* diff --git a/include/config_W7OLMC.h b/include/config_W7OLMC.h index abaea00..6481764 100644 --- a/include/config_W7OLMC.h +++ b/include/config_W7OLMC.h @@ -70,7 +70,7 @@ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_VPD | CFG_CMD_REGINFO) + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include diff --git a/include/config_W7OLMG.h b/include/config_W7OLMG.h index 0e8ec33..f93db94 100644 --- a/include/config_W7OLMG.h +++ b/include/config_W7OLMG.h @@ -75,7 +75,7 @@ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_VPD | CFG_CMD_REGINFO | \ + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \ CFG_CMD_DTT) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */