From: wdenk Date: Sun, 7 Jul 2002 16:20:57 +0000 (+0000) Subject: Patch by Stefan Roese, 28 Jun 2002: X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=5223ba486f0a2d0090bf18a289c2eea60c547d87;p=users%2Frw%2Fppcboot.git Patch by Stefan Roese, 28 Jun 2002: - CPCI4052 (Version 2) changed to 256KByte PPCBoot size. - ppc405: sdram init code (for onboard soldered sdram bank0) ported from assembler to C and moved from board to cpu directory (define CONFIG_SDRAM_BANK0). Now init.S in board directory isn't needed any more (see CPCI405). --- diff --git a/CHANGELOG b/CHANGELOG index 7e6e35b..f343409 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,13 @@ Modifications for 1.2.0: ====================================================================== +* Patch by Stefan Roese, 28 Jun 2002: +- CPCI4052 (Version 2) changed to 256KByte PPCBoot size. +- ppc405: sdram init code (for onboard soldered sdram bank0) + ported from assembler to C and moved from board to cpu directory + (define CONFIG_SDRAM_BANK0). Now init.S in board directory isn't + needed any more (see CPCI405). + * Patch by Pierre Aubert / Steven Scholz: Remove duplicate / broken code in cpu/mpc8xx/fec.c diff --git a/Makefile b/Makefile index e4c4a6d..f2105ee 100644 --- a/Makefile +++ b/Makefile @@ -525,6 +525,7 @@ CPCI4052_config: unconfig echo "BOARD = cpci405" >>config.mk ; \ echo "CPU = ppc4xx" >>config.mk ; \ echo "VENDOR = esd" >>config.mk ; \ + echo "TARGET = $(@:_config=)" >>config.mk ; \ echo "#include " >config.h CPCIISER4_config: unconfig diff --git a/board/esd/adciop/ppcboot.lds.debug b/board/esd/adciop/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/adciop/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/ar405/ppcboot.lds.debug b/board/esd/ar405/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/ar405/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/canbt/ppcboot.lds.debug b/board/esd/canbt/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/canbt/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 12b2fa8..39d2fec 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o -SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 83f07fe..05d4240 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -22,8 +22,11 @@ # # -# esd ADCIOP boards +# esd CPCI405 boards # -#TEXT_BASE = 0xFFFE0000 +ifeq ($(TARGET),CPCI4052) +TEXT_BASE = 0xFFFC0000 +else TEXT_BASE = 0xFFFD0000 +endif diff --git a/board/esd/cpci405/init.S b/board/esd/cpci405/init.S deleted file mode 100644 index 1cad0bd..0000000 --- a/board/esd/cpci405/init.S +++ /dev/null @@ -1,347 +0,0 @@ -//------------------------------------------------------------------------------+ -// -// This source code has been made available to you by IBM on an AS-IS -// basis. Anyone receiving this source is licensed under IBM -// copyrights to use it in any way he or she deems fit, including -// copying it, modifying it, compiling it, and redistributing it either -// with or without modifications. No license under IBM patents or -// patent applications is to be implied by the copyright license. -// -// Any user of this software should understand that IBM cannot provide -// technical support for this software and will not be responsible for -// any consequences resulting from the use of this software. -// -// Any person who transfers this source code or any derivative work -// must include the IBM copyright notice, this paragraph, and the -// preceding two paragraphs in the transferred software. -// -// COPYRIGHT I B M CORPORATION 1995 -// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -//------------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Function: ext_bus_cntlr_init -// Description: Initializes the External Bus Controller for the external -// peripherals. IMPORTANT: For pass1 this code must run from -// cache since you can not reliably change a peripheral banks -// timing register (pbxap) while running code from that bank. -// For ex., since we are running from ROM on bank 0, we can NOT -// execute the code that modifies bank 0 timings from ROM, so -// we run it from cache. -// Bank 0 - Flash bank 0 -// Bank 1 - Flash bank 1 -// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400) -// Bank 3 - IDE (CompactFlash) -// Bank 4 - Quart -// Bank 5 - not used -// Bank 6 - not used -// Bank 7 - not used -//----------------------------------------------------------------------------- -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#define MAGIC0 0x00000000 -#define MAGIC1 0x11111111 -#define MAGIC2 0x22222222 -#define MAGIC3 0x33333333 -#define MAGIC4 0x44444444 - -#define ADDR_ZERO 0x00000000 -#define ADDR_400 0x00000400 -#define ADDR_08MB 0x00800000 -#define ADDR_16MB 0x01000000 -#define ADDR_32MB 0x02000000 -#define ADDR_64MB 0x04000000 - -#include -#include - -#include -#include - - -//----------------------------------------------------------------------------- -// Function: sdram_init -// Description: Configures SDRAM memory banks. -// Auto Memory Configuration option reads the SDRAM EEPROM -// via the IIC bus and then configures the SDRAM memory -// banks appropriately. If Auto Memory Configuration is -// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is -// plugged, ie. the DIMM that shipped wih the Eval board. -//----------------------------------------------------------------------------- - .globl sdram_init - -sdram_init: - - mflr r31 - - //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0008 - ori r4,r4,0x4001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. - // To set the appropriate timings, we need to know the SDRAM speed. - // We can use the PLB speed since the SDRAM speed is the same as - // the PLB speed. The PLB speed is the FBK divider times the - // 405GP reference clock, which on the Walnut board is 33Mhz. - // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is - // 100Mhz; if FBK is 3, SDRAM is 133Mhz. - // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and - // maybe 133Mhz. - //------------------------------------------------------------------- - mfdcr r5,strap // determine FBK divider - // via STRAP reg to calc PLB speed. - // SDRAM speed is the same as the PLB - // speed. - rlwinm r4,r5,4,0x3 // get FBK divide bits - -..chk_66: - cmpi %cr0,0,r4,0x1 - bne ..chk_100 - addis r6,0,0x0085 // SDTR1 value for 66Mhz - ori r6,r6,0x4005 - addis r7,0,0x03F8 // RTR value for 66Mhz - b ..sdram_ok -..chk_100: - cmpi %cr0,0,r4,0x2 - bne ..chk_133 - addis r6,0,0x0086 // SDTR1 value for 100Mhz - ori r6,r6,0x400D - addis r7,0,0x05F0 // RTR value for 100Mhz - b ..sdram_ok -..chk_133: - addis r6,0,0x0107 // SDTR1 value for 133Mhz - ori r6,r6,0x4015 - addis r7,0,0x07F0 // RTR value for 133Mhz - -..sdram_ok: - //------------------------------------------------------------------- - // Set SDTR1 - //------------------------------------------------------------------- - addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 - - //------------------------------------------------------------------- - // Set RTR - //------------------------------------------------------------------- - addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 - - //------------------------------------------------------------------- - // Delay to ensure 200usec have elapsed since reset. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - //------------------------------------------------------------------- - addis r3,0,0x0000 - ori r3,r3,0xA000 // ensure 200usec have passed since reset - mtctr r3 -..spinlp2: - bdnz ..spinlp2 // spin loop - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Delay to ensure 10msec have elapsed since reset. This is - // required for the MPC952 to stabalize. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles - // This delay should occur before accessing SDRAM. - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp3: - bdnz ..spinlp3 // spin loop - - //------------------------------------------------------------------- - // Test if 64MByte is ok. - //------------------------------------------------------------------- - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - stw r3,0x00(r4) // store magic at 0 - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - stw r3,0x00(r4) // store magic at 8MB - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - stw r3,0x00(r4) // store magic at 16MB - addis r3,0,MAGIC3@h - ori r3,r3,MAGIC3@l - addis r4,0,ADDR_32MB@h - ori r4,r4,ADDR_32MB@l - stw r3,0x00(r4) // store magic at 32MB - - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - lwz r5,0x00(r4) // load from 0 - cmplw 0,r3,r5 - bne ..chk_32mb - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - lwz r5,0x00(r4) // load from 8mb - cmplw 0,r3,r5 - bne ..chk_32mb - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - lwz r5,0x00(r4) // load from 8mb - beq ..sdram_done - -..chk_32mb: - //------------------------------------------------------------------- - // Disable memory controller. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x0000 // set DC_EN=0 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0006 - ori r4,r4,0x2001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Wait some time - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp4: - bdnz ..spinlp4 // spin loop - - //------------------------------------------------------------------- - // Test if 32MByte is ok. - //------------------------------------------------------------------- - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - stw r3,0x00(r4) // store magic at 0 - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_400@h - ori r4,r4,ADDR_400@l - stw r3,0x00(r4) // store magic at 0x400 - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - stw r3,0x00(r4) // store magic at 8MB - addis r3,0,MAGIC3@h - ori r3,r3,MAGIC3@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - stw r3,0x00(r4) // store magic at 16MB - - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - lwz r5,0x00(r4) // load from 0 - cmplw 0,r3,r5 - bne ..chk_16mb - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_400@h - ori r4,r4,ADDR_400@l - lwz r5,0x00(r4) // load from 0x400 - cmplw 0,r3,r5 - bne ..chk_16mb - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - lwz r5,0x00(r4) // load from 8mb - cmplw 0,r3,r5 - beq ..sdram_done - -..chk_16mb: - //------------------------------------------------------------------- - // Disable memory controller. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x0000 // set DC_EN=0 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // 16 MB is left. - // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0004 - ori r4,r4,0x6001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Wait some time - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp5: - bdnz ..spinlp5 // spin loop - -..sdram_done: - mtlr r31 // restore lr - blr diff --git a/board/esd/cpci405/ppcboot.lds b/board/esd/cpci405/ppcboot.lds index cbb77e4..0b72293 100644 --- a/board/esd/cpci405/ppcboot.lds +++ b/board/esd/cpci405/ppcboot.lds @@ -62,7 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/esd/cpci405/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) cpu/ppc4xx/serial.o (.text) diff --git a/board/esd/cpci405/ppcboot.lds.debug b/board/esd/cpci405/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/cpci405/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/cpciiser4/ppcboot.lds.debug b/board/esd/cpciiser4/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/cpciiser4/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/dasa_sim/ppcboot.lds.debug b/board/esd/dasa_sim/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/dasa_sim/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile index df19495..1123673 100644 --- a/board/esd/du405/Makefile +++ b/board/esd/du405/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o -SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/esd/du405/init.S b/board/esd/du405/init.S deleted file mode 100644 index bef6dc5..0000000 --- a/board/esd/du405/init.S +++ /dev/null @@ -1,163 +0,0 @@ -//------------------------------------------------------------------------------+ -// -// This source code has been made available to you by IBM on an AS-IS -// basis. Anyone receiving this source is licensed under IBM -// copyrights to use it in any way he or she deems fit, including -// copying it, modifying it, compiling it, and redistributing it either -// with or without modifications. No license under IBM patents or -// patent applications is to be implied by the copyright license. -// -// Any user of this software should understand that IBM cannot provide -// technical support for this software and will not be responsible for -// any consequences resulting from the use of this software. -// -// Any person who transfers this source code or any derivative work -// must include the IBM copyright notice, this paragraph, and the -// preceding two paragraphs in the transferred software. -// -// COPYRIGHT I B M CORPORATION 1995 -// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -//------------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Function: ext_bus_cntlr_init -// Description: Initializes the External Bus Controller for the external -// peripherals. IMPORTANT: For pass1 this code must run from -// cache since you can not reliably change a peripheral banks -// timing register (pbxap) while running code from that bank. -// For ex., since we are running from ROM on bank 0, we can NOT -// execute the code that modifies bank 0 timings from ROM, so -// we run it from cache. -// Bank 0 - Flash bank 0 -// Bank 1 - Flash bank 1 -// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400) -// Bank 3 - IDE (CompactFlash) -// Bank 4 - Quart -// Bank 5 - not used -// Bank 6 - not used -// Bank 7 - not used -//----------------------------------------------------------------------------- -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - - -//----------------------------------------------------------------------------- -// Function: sdram_init -// Description: Configures SDRAM memory banks. -// Auto Memory Configuration option reads the SDRAM EEPROM -// via the IIC bus and then configures the SDRAM memory -// banks appropriately. If Auto Memory Configuration is -// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is -// plugged, ie. the DIMM that shipped wih the Eval board. -//----------------------------------------------------------------------------- - .globl sdram_init - -sdram_init: - - mflr r31 - - //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0004 - ori r4,r4,0x6001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. - // To set the appropriate timings, we need to know the SDRAM speed. - // We can use the PLB speed since the SDRAM speed is the same as - // the PLB speed. The PLB speed is the FBK divider times the - // 405GP reference clock, which on the Walnut board is 33Mhz. - // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is - // 100Mhz; if FBK is 3, SDRAM is 133Mhz. - // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and - // maybe 133Mhz. - //------------------------------------------------------------------- - mfdcr r5,strap // determine FBK divider - // via STRAP reg to calc PLB speed. - // SDRAM speed is the same as the PLB - // speed. - rlwinm r4,r5,4,0x3 // get FBK divide bits - -..chk_66: - cmpi %cr0,0,r4,0x1 - bne ..chk_100 - addis r6,0,0x0085 // SDTR1 value for 66Mhz - ori r6,r6,0x4005 - addis r7,0,0x03F8 // RTR value for 66Mhz - b ..sdram_ok -..chk_100: - cmpi %cr0,0,r4,0x2 - bne ..chk_133 - addis r6,0,0x0086 // SDTR1 value for 100Mhz - ori r6,r6,0x400D - addis r7,0,0x05F0 // RTR value for 100Mhz - b ..sdram_ok -..chk_133: - addis r6,0,0x0107 // SDTR1 value for 133Mhz - ori r6,r6,0x4015 - addis r7,0,0x07F0 // RTR value for 133Mhz - -..sdram_ok: - //------------------------------------------------------------------- - // Set SDTR1 - //------------------------------------------------------------------- - addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 - - //------------------------------------------------------------------- - // Set RTR - //------------------------------------------------------------------- - addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 - - //------------------------------------------------------------------- - // Delay to ensure 200usec have elapsed since reset. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - //------------------------------------------------------------------- - addis r3,0,0x0000 - ori r3,r3,0xA000 // ensure 200usec have passed since reset - mtctr r3 -..spinlp2: - bdnz ..spinlp2 // spin loop - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Delay to ensure 10msec have elapsed since reset. This is - // required for the MPC952 to stabalize. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles - // This delay should occur before accessing SDRAM. - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp3: - bdnz ..spinlp3 // spin loop - - mtlr r31 // restore lr - blr diff --git a/board/esd/du405/ppcboot.lds b/board/esd/du405/ppcboot.lds index b6de8e3..7288c5f 100644 --- a/board/esd/du405/ppcboot.lds +++ b/board/esd/du405/ppcboot.lds @@ -62,7 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/esd/du405/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) cpu/ppc4xx/serial.o (.text) diff --git a/board/esd/du405/ppcboot.lds.debug b/board/esd/du405/ppcboot.lds.debug deleted file mode 100644 index 8e59f7f..0000000 --- a/board/esd/du405/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/ocrtc/ppcboot.lds.debug b/board/esd/ocrtc/ppcboot.lds.debug deleted file mode 100644 index 9e9ff00..0000000 --- a/board/esd/ocrtc/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile index 12b2fa8..39d2fec 100644 --- a/board/esd/pci405/Makefile +++ b/board/esd/pci405/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o -SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/esd/pci405/init.S b/board/esd/pci405/init.S deleted file mode 100644 index 1cad0bd..0000000 --- a/board/esd/pci405/init.S +++ /dev/null @@ -1,347 +0,0 @@ -//------------------------------------------------------------------------------+ -// -// This source code has been made available to you by IBM on an AS-IS -// basis. Anyone receiving this source is licensed under IBM -// copyrights to use it in any way he or she deems fit, including -// copying it, modifying it, compiling it, and redistributing it either -// with or without modifications. No license under IBM patents or -// patent applications is to be implied by the copyright license. -// -// Any user of this software should understand that IBM cannot provide -// technical support for this software and will not be responsible for -// any consequences resulting from the use of this software. -// -// Any person who transfers this source code or any derivative work -// must include the IBM copyright notice, this paragraph, and the -// preceding two paragraphs in the transferred software. -// -// COPYRIGHT I B M CORPORATION 1995 -// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -//------------------------------------------------------------------------------- - -//----------------------------------------------------------------------------- -// Function: ext_bus_cntlr_init -// Description: Initializes the External Bus Controller for the external -// peripherals. IMPORTANT: For pass1 this code must run from -// cache since you can not reliably change a peripheral banks -// timing register (pbxap) while running code from that bank. -// For ex., since we are running from ROM on bank 0, we can NOT -// execute the code that modifies bank 0 timings from ROM, so -// we run it from cache. -// Bank 0 - Flash bank 0 -// Bank 1 - Flash bank 1 -// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400) -// Bank 3 - IDE (CompactFlash) -// Bank 4 - Quart -// Bank 5 - not used -// Bank 6 - not used -// Bank 7 - not used -//----------------------------------------------------------------------------- -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#define MAGIC0 0x00000000 -#define MAGIC1 0x11111111 -#define MAGIC2 0x22222222 -#define MAGIC3 0x33333333 -#define MAGIC4 0x44444444 - -#define ADDR_ZERO 0x00000000 -#define ADDR_400 0x00000400 -#define ADDR_08MB 0x00800000 -#define ADDR_16MB 0x01000000 -#define ADDR_32MB 0x02000000 -#define ADDR_64MB 0x04000000 - -#include -#include - -#include -#include - - -//----------------------------------------------------------------------------- -// Function: sdram_init -// Description: Configures SDRAM memory banks. -// Auto Memory Configuration option reads the SDRAM EEPROM -// via the IIC bus and then configures the SDRAM memory -// banks appropriately. If Auto Memory Configuration is -// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is -// plugged, ie. the DIMM that shipped wih the Eval board. -//----------------------------------------------------------------------------- - .globl sdram_init - -sdram_init: - - mflr r31 - - //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0008 - ori r4,r4,0x4001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. - // To set the appropriate timings, we need to know the SDRAM speed. - // We can use the PLB speed since the SDRAM speed is the same as - // the PLB speed. The PLB speed is the FBK divider times the - // 405GP reference clock, which on the Walnut board is 33Mhz. - // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is - // 100Mhz; if FBK is 3, SDRAM is 133Mhz. - // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and - // maybe 133Mhz. - //------------------------------------------------------------------- - mfdcr r5,strap // determine FBK divider - // via STRAP reg to calc PLB speed. - // SDRAM speed is the same as the PLB - // speed. - rlwinm r4,r5,4,0x3 // get FBK divide bits - -..chk_66: - cmpi %cr0,0,r4,0x1 - bne ..chk_100 - addis r6,0,0x0085 // SDTR1 value for 66Mhz - ori r6,r6,0x4005 - addis r7,0,0x03F8 // RTR value for 66Mhz - b ..sdram_ok -..chk_100: - cmpi %cr0,0,r4,0x2 - bne ..chk_133 - addis r6,0,0x0086 // SDTR1 value for 100Mhz - ori r6,r6,0x400D - addis r7,0,0x05F0 // RTR value for 100Mhz - b ..sdram_ok -..chk_133: - addis r6,0,0x0107 // SDTR1 value for 133Mhz - ori r6,r6,0x4015 - addis r7,0,0x07F0 // RTR value for 133Mhz - -..sdram_ok: - //------------------------------------------------------------------- - // Set SDTR1 - //------------------------------------------------------------------- - addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 - - //------------------------------------------------------------------- - // Set RTR - //------------------------------------------------------------------- - addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 - - //------------------------------------------------------------------- - // Delay to ensure 200usec have elapsed since reset. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - //------------------------------------------------------------------- - addis r3,0,0x0000 - ori r3,r3,0xA000 // ensure 200usec have passed since reset - mtctr r3 -..spinlp2: - bdnz ..spinlp2 // spin loop - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Delay to ensure 10msec have elapsed since reset. This is - // required for the MPC952 to stabalize. Assume worst - // case that the core is running 200Mhz: - // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles - // This delay should occur before accessing SDRAM. - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp3: - bdnz ..spinlp3 // spin loop - - //------------------------------------------------------------------- - // Test if 64MByte is ok. - //------------------------------------------------------------------- - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - stw r3,0x00(r4) // store magic at 0 - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - stw r3,0x00(r4) // store magic at 8MB - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - stw r3,0x00(r4) // store magic at 16MB - addis r3,0,MAGIC3@h - ori r3,r3,MAGIC3@l - addis r4,0,ADDR_32MB@h - ori r4,r4,ADDR_32MB@l - stw r3,0x00(r4) // store magic at 32MB - - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - lwz r5,0x00(r4) // load from 0 - cmplw 0,r3,r5 - bne ..chk_32mb - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - lwz r5,0x00(r4) // load from 8mb - cmplw 0,r3,r5 - bne ..chk_32mb - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - lwz r5,0x00(r4) // load from 8mb - beq ..sdram_done - -..chk_32mb: - //------------------------------------------------------------------- - // Disable memory controller. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x0000 // set DC_EN=0 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0006 - ori r4,r4,0x2001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Wait some time - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp4: - bdnz ..spinlp4 // spin loop - - //------------------------------------------------------------------- - // Test if 32MByte is ok. - //------------------------------------------------------------------- - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - stw r3,0x00(r4) // store magic at 0 - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_400@h - ori r4,r4,ADDR_400@l - stw r3,0x00(r4) // store magic at 0x400 - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - stw r3,0x00(r4) // store magic at 8MB - addis r3,0,MAGIC3@h - ori r3,r3,MAGIC3@l - addis r4,0,ADDR_16MB@h - ori r4,r4,ADDR_16MB@l - stw r3,0x00(r4) // store magic at 16MB - - addis r3,0,MAGIC0@h - ori r3,r3,MAGIC0@l - addis r4,0,ADDR_ZERO@h - ori r4,r4,ADDR_ZERO@l - lwz r5,0x00(r4) // load from 0 - cmplw 0,r3,r5 - bne ..chk_16mb - addis r3,0,MAGIC1@h - ori r3,r3,MAGIC1@l - addis r4,0,ADDR_400@h - ori r4,r4,ADDR_400@l - lwz r5,0x00(r4) // load from 0x400 - cmplw 0,r3,r5 - bne ..chk_16mb - addis r3,0,MAGIC2@h - ori r3,r3,MAGIC2@l - addis r4,0,ADDR_08MB@h - ori r4,r4,ADDR_08MB@l - lwz r5,0x00(r4) // load from 8mb - cmplw 0,r3,r5 - beq ..sdram_done - -..chk_16mb: - //------------------------------------------------------------------- - // Disable memory controller. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x0000 // set DC_EN=0 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // 16 MB is left. - // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) - //------------------------------------------------------------------- - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,0x0004 - ori r4,r4,0x6001 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Set memory controller options reg, MCOPT1. - // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - // read/prefetch. - //------------------------------------------------------------------- - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 // set DC_EN=1 - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - //------------------------------------------------------------------- - // Wait some time - //------------------------------------------------------------------- - addis r3,0,0x001E - ori r3,r3,0x8480 // ensure 10msec have passed since reset - mtctr r3 -..spinlp5: - bdnz ..spinlp5 // spin loop - -..sdram_done: - mtlr r31 // restore lr - blr diff --git a/board/esd/pci405/ppcboot.lds b/board/esd/pci405/ppcboot.lds index 5a94fa1..0b72293 100644 --- a/board/esd/pci405/ppcboot.lds +++ b/board/esd/pci405/ppcboot.lds @@ -62,7 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/esd/pci405/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) cpu/ppc4xx/serial.o (.text) diff --git a/board/esd/pci405/ppcboot.lds.debug b/board/esd/pci405/ppcboot.lds.debug deleted file mode 100644 index 35d9f7c..0000000 --- a/board/esd/pci405/ppcboot.lds.debug +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} - diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 53a5933..12f1fdf 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -29,7 +29,7 @@ START = start.o resetvec.o kgdb.o AOBJS = dcr.o COBJS = traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \ 405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o \ - spd_sdram.o + spd_sdram.o sdram.o OBJS = $(AOBJS) $(COBJS) all: .depend $(START) $(LIB) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c new file mode 100644 index 0000000..5b1fca0 --- /dev/null +++ b/cpu/ppc4xx/sdram.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +#ifdef CONFIG_SDRAM_BANK0 + + +#define MAGIC0 0x00000000 +#define MAGIC1 0x11111111 +#define MAGIC2 0x22222222 +#define MAGIC3 0x33333333 +#define MAGIC4 0x44444444 + +#define ADDR_ZERO 0x00000000 +#define ADDR_400 0x00000400 +#define ADDR_08MB 0x00800000 +#define ADDR_16MB 0x01000000 +#define ADDR_32MB 0x02000000 +#define ADDR_64MB 0x04000000 + +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + + +/*----------------------------------------------------------------------- + */ +void sdram_init(void) +{ + ulong speed; + ulong sdtr1; + ulong rtr; + + /* + * Determine SDRAM speed + */ + speed = get_bus_freq(0); /* input parameter not needed on ppc4xx systems */ + + /* + * Support for 100MHz and 133MHz SDRAM + */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ + sdtr1 = 0x01074015; + rtr = 0x07f00000; + } else { + /* + * default: 100 MHz SDRAM + */ + sdtr1 = 0x0086400d; + rtr = 0x05f00000; + } + + /* + * Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) + */ + mtsdram0(mem_mb0cf, 0x00084001); + + mtsdram0(mem_sdtr1, sdtr1); + mtsdram0(mem_rtr, rtr); + + /* + * Wait for 200us + */ + udelay(200); + + /* + * Set memory controller options reg, MCOPT1. + * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + * read/prefetch. + */ + mtsdram0(mem_mcopt1, 0x80800000); + + /* + * Wait for 10ms + */ + udelay(10000); + + /* + * Test if 64 MByte are equipped (mirror test) + */ + *(volatile ulong *)ADDR_ZERO = MAGIC0; + *(volatile ulong *)ADDR_08MB = MAGIC1; + *(volatile ulong *)ADDR_16MB = MAGIC2; + *(volatile ulong *)ADDR_32MB = MAGIC3; + + if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && + (*(volatile ulong *)ADDR_08MB == MAGIC1) && + (*(volatile ulong *)ADDR_16MB == MAGIC2)) { + /* + * OK, 64MB detected -> all done + */ + return; + } + + /* + * Now test for 32 MByte... + */ + + /* + * Disable memory controller. + */ + mtsdram0(mem_mcopt1, 0x00000000); + + /* + * Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) + */ + mtsdram0(mem_mb0cf, 0x00062001); + + /* + * Set memory controller options reg, MCOPT1. + * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + * read/prefetch. + */ + mtsdram0(mem_mcopt1, 0x80800000); + + /* + * Wait for 10ms + */ + udelay(10000); + + /* + * Test if 32 MByte are equipped (mirror test) + */ + *(volatile ulong *)ADDR_ZERO = MAGIC0; + *(volatile ulong *)ADDR_400 = MAGIC1; + *(volatile ulong *)ADDR_08MB = MAGIC2; + *(volatile ulong *)ADDR_16MB = MAGIC3; + + if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && + (*(volatile ulong *)ADDR_400 == MAGIC1) && + (*(volatile ulong *)ADDR_08MB == MAGIC2)) { + /* + * OK, 32MB detected -> all done + */ + return; + } + + /* + * Setup for 16 MByte... + */ + + /* + * Disable memory controller. + */ + mtsdram0(mem_mcopt1, 0x00000000); + + /* + * Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) + */ + mtsdram0(mem_mb0cf, 0x00046001); + + /* + * Set memory controller options reg, MCOPT1. + * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + * read/prefetch. + */ + mtsdram0(mem_mcopt1, 0x80800000); + + /* + * Wait for 10ms + */ + udelay(10000); +} + +#endif /* CONFIG_SDRAM_BANK0 */ diff --git a/include/config_AR405.h b/include/config_AR405.h index 22939a2..cfb32c8 100644 --- a/include/config_AR405.h +++ b/include/config_AR405.h @@ -192,10 +192,6 @@ #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in RAM) */ diff --git a/include/config_CANBT.h b/include/config_CANBT.h index f0a3dcc..af5e0bb 100644 --- a/include/config_CANBT.h +++ b/include/config_CANBT.h @@ -184,10 +184,6 @@ #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in RAM) */ diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h index ad5abd5..cbd05ce 100644 --- a/include/config_CPCI405.h +++ b/include/config_CPCI405.h @@ -84,6 +84,8 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + /* * Miscellaneous configurable options */ diff --git a/include/config_CPCI4052.h b/include/config_CPCI4052.h index 913ae46..b37fb7d 100644 --- a/include/config_CPCI4052.h +++ b/include/config_CPCI4052.h @@ -89,6 +89,8 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + /* * Miscellaneous configurable options */ @@ -182,9 +184,9 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ /* diff --git a/include/config_DU405.h b/include/config_DU405.h index 1e2ca73..242b03b 100644 --- a/include/config_DU405.h +++ b/include/config_DU405.h @@ -72,6 +72,8 @@ #define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ #define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + /* * Miscellaneous configurable options */ diff --git a/include/config_PCI405.h b/include/config_PCI405.h index 1886676..8cf0856 100644 --- a/include/config_PCI405.h +++ b/include/config_PCI405.h @@ -85,6 +85,8 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + /* * Miscellaneous configurable options */