From: wdenk Date: Mon, 15 Oct 2001 21:41:42 +0000 (+0000) Subject: * Cleanup of Sandpoint (MPC8240) code X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=493b6d9e03a45c452a276278caee163365ee5a3f;p=users%2Frw%2Fppcboot.git * Cleanup of Sandpoint (MPC8240) code Patch by Thomas Koeller, 15 Oct 2001 * Cleanup of 40x code, adapting it to new "mii" command Patch by Stefan Roese, 15 Oct 2001 --- diff --git a/CHANGELOG b/CHANGELOG index 7996642..0a8e95c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -56,6 +56,12 @@ To do: Modifications for 1.0.6: ====================================================================== +* Cleanup of Sandpoint (MPC8240) code + Patch by Thomas Koeller, 15 Oct 2001 + +* Cleanup of 40x code, adapting it to new "mii" command + Patch by Stefan Roese, 15 Oct 2001 + * Added CFG_DEFAULT_IMMR: Default address of the IMMR after system reset. Needed on some 8260 systems (MPC8260ADS and RPXsuper) to be able to adjust the position of the IMMR register after a reset. @@ -148,7 +154,7 @@ Modifications for 1.0.5: * Modified default configuration for sbc8260 Patch by Jon Diekema, 4 Sep 2001 -* Changed default behavious in case of crashes: automatically reboot +* Changed default behaviour in case of crashes: automatically reboot on panic now (see description of CONFIG_PANIC_HANG in the README file) diff --git a/CREDITS b/CREDITS index 8e0dc60..abd686b 100644 --- a/CREDITS +++ b/CREDITS @@ -102,6 +102,10 @@ N: Yoo. Jonghoon E: yooth@ipone.co.kr D: Added port to the RPXlite board +N: Thomas Koeller +E: tkoeller@gmx.net +D: Port to Motorola Sandpoint 3 (MPC8240) + N: Thomas Lange E: thomas@corelatus.com D: Support for GTH board; lots of PCMCIA fixes diff --git a/board/esd/ar405/config.mk b/board/esd/ar405/config.mk index 83f07fe..b229ec0 100644 --- a/board/esd/ar405/config.mk +++ b/board/esd/ar405/config.mk @@ -22,7 +22,7 @@ # # -# esd ADCIOP boards +# esd AR405 boards # #TEXT_BASE = 0xFFFE0000 diff --git a/board/esd/ar405/ppcboot.lds b/board/esd/ar405/ppcboot.lds index 47d5f49..daa656d 100644 --- a/board/esd/ar405/ppcboot.lds +++ b/board/esd/ar405/ppcboot.lds @@ -83,7 +83,6 @@ SECTIONS common/lists.o (.text) common/board.o (.text) common/main.o (.text) - net/net.o (.text) . = env_offset; common/environment.o(.text) diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile index 99c030c..d86dff8 100644 --- a/board/sandpoint/Makefile +++ b/board/sandpoint/Makefile @@ -25,10 +25,10 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o board_init.o ns16550.o ns87308.o serial.o speed.o -#eepro100.o +OBJS = $(BOARD).o flash.o ns16550.o ns87308.o serial.o speed.o +SOBJS = early_init.o -$(LIB): .depend $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $^ ######################################################################### diff --git a/board/sandpoint/README b/board/sandpoint/README new file mode 100644 index 0000000..95ce858 --- /dev/null +++ b/board/sandpoint/README @@ -0,0 +1,15 @@ +This port of PPCBoot will run on a Motorola Sandpoint 3 development +system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a +snapshot of work in progress and far from being completed. In order +to run it on the target system, it has to be downloaded using the +DINK32 monitor program that came with your Sandpoint system. Please +note that DINK32 does not accept the S-Record file created by the +PPCBoot build process unmodified, because it contains CR/LF line +terminators. You have to strip the CR characters first. There is a +tiny script named 'dinkdl' I created for this purpose. + +The Sandpoint port is based on the work of Rob Taylor, who does not +seem to maintain it any more. I can be reached by mail as +tkoeller@gmx.net. + +Thomas Koeller diff --git a/board/sandpoint/board_init.c b/board/sandpoint/board_init.c deleted file mode 100644 index e69de29..0000000 diff --git a/board/sandpoint/config.mk b/board/sandpoint/config.mk index ccf6830..2a0e685 100644 --- a/board/sandpoint/config.mk +++ b/board/sandpoint/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ # Sandpoint boards # -TEXT_BASE = 0xFE000000 +#TEXT_BASE = 0xFE000000 +TEXT_BASE = 0x00090000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl new file mode 100755 index 0000000..f281452 --- /dev/null +++ b/board/sandpoint/dinkdl @@ -0,0 +1,2 @@ +#! /bin/bash +tr -d "\r" <$1 >/dev/tts/1 diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S new file mode 100644 index 0000000..41bbecf --- /dev/null +++ b/board/sandpoint/early_init.S @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2001 + * Thomas Koeller, tkoeller@gmx.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define __ASSEMBLY__ + +#include +#include +#include +#include + +#if defined(USE_DINK32) + /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ + #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) +#else + #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) +#endif + + .text + + /* Values to program into memory controller registers */ +tbl: .long MCCR1, MCCR1VAL + .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR3 + .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ + (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long MCCR4 + .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CFG_REGISTERD_TYPE_BUFFER << 20) | \ + (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ + (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long MSAR1 + .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR1 + .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MSAR2 + .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR2 + .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR1 + .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR1 + .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR2 + .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR2 + .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long 0 + + + + /* + * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This + * must be done in assembly, since we have no stack at this point. + */ + .global early_init_f +early_init_f: + mflr r10 + + /* basic memory controller configuration */ + lis r3, CONFIG_ADDR_HIGH + lis r4, CONFIG_DATA_HIGH + bl lab +lab: mflr r5 + lwzu r0, tbl - lab(r5) +loop: lwz r1, 4(r5) + stwbrx r0, 0, r3 + eieio + stwbrx r1, 0, r4 + eieio + lwzu r0, 8(r5) + cmpli cr0, 0, r0, 0 + bne cr0, loop + + /* set bank enable bits */ + lis r0, MBER@h + ori r0, 0, MBER@l + li r1, CFG_BANK_ENABLE + stwbrx r0, 0, r3 + eieio + stb r1, 0(r4) + eieio + + /* delay loop */ + lis r0, 0x0003 + mtctr r0 +delay: bdnz delay + + /* enable memory controller */ + lis r0, MCCR1@h + ori r0, 0, MCCR1@l + stwbrx r0, 0, r3 + eieio + lwbrx r0, 0, r4 + oris r0, 0, MCCR1_MEMGO@h + stwbrx r0, 0, r4 + eieio + + /* set up stack pointer */ + lis r1, CFG_INIT_SP_OFFSET@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + mtlr r10 + blr + diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c index 8dfa44b..e113289 100644 --- a/board/sandpoint/flash.c +++ b/board/sandpoint/flash.c @@ -27,12 +27,11 @@ #include #include "w83c553f.h" -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions */ -ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); static void flash_get_offsets (ulong base, flash_info_t *info); @@ -47,54 +46,131 @@ static void flash_get_offsets (ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +static int byte_parity_odd(unsigned char x) __attribute__ ((const)); +static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); + +typedef struct { - unsigned long size; - int i; - unsigned long base; - register unsigned long temp; + FLASH_WORD_SIZE extval; + unsigned short intval; +} map_entry; - /* Init: no FLASHes known */ - for (i=0; i> 4; + x ^= x >> 2; + x ^= x >> 1; + return (x & 0x1) != 0; +} - size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); + +static unsigned long +flash_id(unsigned char mfct, unsigned char chip) +{ + static const map_entry mfct_map[] = + { + {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, + {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, + {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, + {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, + {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, + {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} + }; + + static const map_entry chip_map[] = + { + {AMD_ID_F040B, FLASH_AM040} + }; + + const map_entry *p; + unsigned long result = FLASH_UNKNOWN; + + /* find chip id */ + for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) + if(p->extval == chip) + { + result = FLASH_VENDMASK | p->intval; + break; } + /* find vendor id */ + for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) + if(p->extval == mfct) + { + result &= ~FLASH_VENDMASK; + result |= (unsigned long) p->intval << 16; + break; + } - flash_get_offsets (base, &flash_info[0]); + return result; +} - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - base + size-CFG_MONITOR_LEN, - base + size - 1, - &flash_info[0]); - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; +unsigned long +flash_init(void) +{ + unsigned long i; + static const ulong flash_banks[] = CFG_FLASH_BANKS; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info_t * const pflinfo = &flash_info[i]; + pflinfo->flash_id = FLASH_UNKNOWN; + pflinfo->size = 0; + pflinfo->sector_count = 0; + } + + /* Enable writes to Sandpoint flash */ + { + register unsigned char temp; + CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + temp &= ~0x20; /* clear BIOSWP bit */ + CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + } + + for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) + { + flash_info_t * const pflinfo = &flash_info[i]; + const unsigned long base_address = flash_banks[i]; + volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; + + /* write autoselect sequence */ + flash[0x5555] = 0xaa; + flash[0x2aaa] = 0x55; + flash[0x5555] = 0x90; + __asm__ __volatile__("sync"); + + pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); + + switch(pflinfo->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 8; + for(i = 0; i < 8; i++) + { + pflinfo->start[i] = base_address + 0x00010000 * i; + pflinfo->protect[i] = flash[(i << 16) | 0x2]; + } + break; + } - flash_info[0].size = size; + /* reset device to read mode */ + flash[0x0000] = 0xf0; + __asm__ __volatile__("sync"); + } - return (size); + return flash_info[0].size; } -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void +flash_get_offsets (ulong base, flash_info_t *info) { int i; @@ -129,103 +205,90 @@ static void flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void +flash_print_info(flash_info_t *info) { - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if(info->flash_id != FLASH_UNKNOWN) + { + switch(info->flash_id & FLASH_VENDMASK) + { + case FLASH_MAN_AMD: mfct = "AMD"; break; + case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; + case FLASH_MAN_SST: mfct = "SST"; break; + case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; + case FLASH_MAN_INTEL: mfct = "Intel"; break; } - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + switch(info->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; + case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; + case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; + case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; + case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; + case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; + case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; + case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; + case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; + case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; } + } - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + printf( + "\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, + type, + info->size >> 10, + info->sector_count + ); - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - info->protect[i] ? " (RO)" : " " -#else - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " -#endif - ); - } - printf ("\n"); -} + printf (" Sector Start Addresses:"); -/*----------------------------------------------------------------------- - */ + for (i = 0; i < info->sector_count; i++) + { + unsigned long size; + unsigned int erased; + unsigned long * flash = (unsigned long *) info->start[i]; + /* + * Check if whole sector is erased + */ + size = + (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for( + flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++ + ) + erased = *flash == ~0x0UL; + + printf( + "%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", + info->protect[i] ? "RO" : " " + ); + } + + puts("\n"); +} -/*----------------------------------------------------------------------- - */ +#if 0 /* * The following code cannot be run from FLASH! */ -ulong flash_get_size (vu_long *addr, flash_info_t *info) +ulong +flash_get_size (vu_long *addr, flash_info_t *info) { short i; FLASH_WORD_SIZE value; @@ -297,19 +360,7 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif + case (FLASH_WORD_SIZE)SST_ID_xF800A: info->flash_id += FLASH_SST800A; info->sector_count = 16; @@ -384,11 +435,11 @@ ulong flash_get_size (vu_long *addr, flash_info_t *info) return (info->size); } +#endif -/*----------------------------------------------------------------------- - */ -void flash_erase (flash_info_t *info, int s_first, int s_last) +void +flash_erase(flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); int flag, prot, sect, l_sect; diff --git a/board/sandpoint/ns16550.c b/board/sandpoint/ns16550.c index 1fb9779..dd83311 100644 --- a/board/sandpoint/ns16550.c +++ b/board/sandpoint/ns16550.c @@ -7,55 +7,58 @@ #include #include "ns16550.h" +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + typedef struct NS16550 *NS16550_t; -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_ISA_IO + COM1), - (NS16550_t) (CFG_ISA_IO + COM2) }; +static const NS16550_t COM_PORTS[2] = + {(NS16550_t) (CFG_ISA_IO + COM1), (NS16550_t) (CFG_ISA_IO + COM2)}; volatile struct NS16550 * NS16550_init(int chan, int baud_divisor) { - volatile struct NS16550 *com_port; - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ - return (com_port); + volatile struct NS16550 *com_port; + com_port = (struct NS16550 *) COM_PORTS[chan]; + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; + return (com_port); } void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor) { - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; } -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c) +void +NS16550_putc(volatile struct NS16550 *com_port, char c) { - while ((com_port->lsr & LSR_THRE) == 0) ; - com_port->thr = c; + while ((com_port->lsr & LSR_THRE) == 0) ; + com_port->thr = c; } -unsigned char +char NS16550_getc(volatile struct NS16550 *com_port) { - while ((com_port->lsr & LSR_DR) == 0) ; - return (com_port->rbr); + while ((com_port->lsr & LSR_DR) == 0) ; + return (com_port->rbr); } -int NS16550_tstc(volatile struct NS16550 *com_port) +int +NS16550_tstc(volatile struct NS16550 *com_port) { - return ((com_port->lsr & LSR_DR) != 0); + return ((com_port->lsr & LSR_DR) != 0); } - - - diff --git a/board/sandpoint/ns16550.h b/board/sandpoint/ns16550.h index 3a28d9d..a298cec 100644 --- a/board/sandpoint/ns16550.h +++ b/board/sandpoint/ns16550.h @@ -11,8 +11,8 @@ struct NS16550 - { - unsigned char rbr; /* 0 */ +{ + char rbr; /* 0 */ unsigned char ier; /* 1 */ unsigned char fcr; /* 2 */ unsigned char lcr; /* 3 */ @@ -20,7 +20,7 @@ struct NS16550 unsigned char lsr; /* 5 */ unsigned char msr; /* 6 */ unsigned char scr; /* 7 */ - }; +}; #define thr rbr #define iir fcr @@ -28,7 +28,7 @@ struct NS16550 #define dlm ier #define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ +#define FCR_RXSR 0x02 /*receiver soft reset*/ #define FCR_TXSR 0x04 /*transmitter soft reset*/ @@ -67,8 +67,8 @@ struct NS16550 #define COM2 0x02F8 volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); +void NS16550_putc(volatile struct NS16550 *com_port, char c); +char NS16550_getc(volatile struct NS16550 *com_port); int NS16550_tstc(volatile struct NS16550 *com_port); void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/sandpoint/ns87308.h b/board/sandpoint/ns87308.h index 14b9f5c..8cb0f03 100644 --- a/board/sandpoint/ns87308.h +++ b/board/sandpoint/ns87308.h @@ -93,7 +93,7 @@ #define LDEV_PARP 0x04 /*Parallel port*/ #define LDEV_UART1 0x05 #define LDEV_UART2 0x06 -#define LDEV_GPIO 0x07 /*Gennerla Purpose IO and chip select output signals*/ +#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ #define LDEV_POWRMAN 0x08 /*Power Managment*/ /*some functions and macro's for doing configuration */ @@ -136,7 +136,7 @@ static inline void write_pgcs_config(unsigned char index, unsigned char data) write_pnp_config(PGCS_DATA, data); } -/* these macrose configure the 3 CS lines +/* these macros configure the 3 CS lines on the sandpoint board these controll NVRAM CS0 is connected to NVRAMCS CS1 is connected to NVRAMAS0 diff --git a/board/sandpoint/ppcboot.lds b/board/sandpoint/ppcboot.lds index 59fc9a2..2d654a4 100644 --- a/board/sandpoint/ppcboot.lds +++ b/board/sandpoint/ppcboot.lds @@ -1,6 +1,6 @@ /* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -23,77 +23,104 @@ OUTPUT_ARCH(powerpc) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); - -MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfe000000 , LENGTH = (0x100000000 - 0xfe000000) -} - +/* Do we need any of these for elf? + __DYNAMIC = 0; */ SECTIONS { - _f_init = .; - PROVIDE(_f_init = .); - _f_init_rom = .; - PROVIDE(_f_init_rom = .); + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8240/start.o (.text) + common/board.o (.text) + ppc/ppcstring.o (.text) + ppc/vsprintf.o (.text) + ppc/crc32.o (.text) + ppc/zlib.o (.text) - .init : { - cpu/mpc8240/start.o (.text) - *(.init) - } > ram - _init_size = SIZEOF(.init); - PROVIDE(_init_size = SIZEOF(.init)); + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) - ENTRY(_start) + *(.text) -/* _ftext = .; - _ftext_rom = .; - _text_size = SIZEOF(.text); - */ - .text : { - *(.text) - *(.got1) - } > ram - .rodata : { *(.rodata) } > ram - .dtors : { *(.dtors) } > ram - .data : { *(.data) } > ram - .sdata : { *(.sdata) } > ram - .sdata2 : { *(.sdata2) - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; *(.fixup) - } > ram - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } - .sbss : { *(.sbss) } > ram - .sbss2 : { *(.sbss2) } > ram - .bss : { *(.bss) } > ram - .debug : { *(.debug) } > ram - .line : { *(.line) } > ram - .symtab : { *(.symtab) } > ram - .shrstrtab : { *(.shstrtab) } > ram - .strtab : { *(.strtab) } > ram - /* .reloc : + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : { *(.got) _GOT2_TABLE_ = .; *(.got2) _FIXUP_TABLE_ = .; *(.fixup) - } > ram - */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } > ram - __stop___ex_table = .; + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; - .ppcenv : + __bss_start = .; + .bss : { - common/environment.o (.ppcenv) - } > ram + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } _end = . ; PROVIDE (end = .); diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index b1a3fb9..9d5e57c 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -22,6 +22,7 @@ */ #include +#include int checkboard (void) { @@ -34,46 +35,55 @@ int checkboard (void) int checkflash (void) { /* TODO: XXX XXX XXX */ - printf ("8 MB ## Test not implemented yet ##\n"); + printf ("## Test not implemented yet ##\n"); return (0); } -long int dram_size (int board_type) +static long +dram_size(void) { - /* No actual initialisation to do - done when setting up PICRs MCCRs ME/SARs etc - * in cpu_init.c - done there to keep init sequence same as Dink. May be able to move some of - * it here and refine the configuration defines to be more high-level, but I haven't had time - * to investigate that yet - */ - #if defined(CFG_MEM_TEST) - - register unsigned long reg; - - //write each mem addr with it's address - for (reg = CFG_MEM_TEST_START; reg < CGF_MEM_TEST_END; reg+=4 - *reg = reg; - - for (reg = CFG_MEM_TEST_START; reg < CGF_MEM_TEST_END; reg+=4 - { - if (*reg != reg) - return -1; - } - #endif - - //TODO: calculate amount of dram..for now just return MEMTEST_END - return CFG_MEMTEST_END; - + static const unsigned long + addressmask = 0x4ff00000, + addressinc = 0x00100000; + long result = 0; + +#if (CFG_BANK_ENABLE & 0x80) + result += (CFG_BANK7_END & addressmask) + addressinc - (CFG_BANK7_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x40) + result += (CFG_BANK6_END & addressmask) + addressinc - (CFG_BANK6_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x20) + result += (CFG_BANK5_END & addressmask) + addressinc - (CFG_BANK5_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x10) + result += (CFG_BANK4_END & addressmask) + addressinc - (CFG_BANK4_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x08) + result += (CFG_BANK3_END & addressmask) + addressinc - (CFG_BANK3_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x04) + result += (CFG_BANK2_END & addressmask) + addressinc - (CFG_BANK2_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x02) + result += (CFG_BANK1_END & addressmask) + addressinc - (CFG_BANK1_START & addressmask); +#endif +#if (CFG_BANK_ENABLE & 0x01) + result += (CFG_BANK0_END & addressmask) + addressinc - (CFG_BANK0_START & addressmask); +#endif + + return result; } long int initdram(int board_type) { -return dram_size(board_type); + return dram_size(); } -/*temporarlyily here: to be removed:*/ +/* temporarily here: to be removed: */ int eth_init(bd_t *bis) diff --git a/board/sandpoint/serial.c b/board/sandpoint/serial.c index ec7afa0..e09dac0 100644 --- a/board/sandpoint/serial.c +++ b/board/sandpoint/serial.c @@ -21,8 +21,11 @@ * MA 02111-1307 USA */ +#include #include "ns16550.h" +#define IDATA (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET) + void initialise_ns87308(void); /* @@ -35,41 +38,46 @@ volatile struct NS16550 *console; void serial_init (unsigned long dummy, int baudrate) { - int clock_divisor = 115200/baudrate; - initialise_ns87308(); - console = NS16550_init(0, clock_divisor); + init_data_t * const idata = IDATA; + const int clock_divisor = 115200/baudrate; + /* initialise_ns87308(); */ + idata->console_addr = NS16550_init(0, clock_divisor); } void serial_putc(const char c) { - NS16550_putc(console, c); + init_data_t * const idata = IDATA; + NS16550_putc((struct NS16550 *) idata->console_addr, c); + if(c == '\n') NS16550_putc((struct NS16550 *) idata->console_addr, '\r'); } void serial_puts (const char *s) { - while (*s) { - serial_putc (*s++); - } + while (*s) { + serial_putc (*s++); + } } - int serial_getc(void) { - return NS16550_getc(console); + init_data_t * const idata = IDATA; + return NS16550_getc((struct NS16550 *) idata->console_addr); } int serial_tstc(void) { - return NS16550_tstc(console); + init_data_t * const idata = IDATA; + return NS16550_tstc((struct NS16550 *) idata->console_addr); } void serial_setbrg (unsigned long dummy, int baudrate) { - int clock_divisor = 115200/baudrate; - NS16550_reinit(console, clock_divisor); + init_data_t * const idata = IDATA; + const int clock_divisor = 115200/baudrate; + NS16550_reinit((struct NS16550 *) idata->console_addr, clock_divisor); } diff --git a/board/sandpoint/speed.c b/board/sandpoint/speed.c index c44297c..5549eb9 100644 --- a/board/sandpoint/speed.c +++ b/board/sandpoint/speed.c @@ -35,47 +35,20 @@ static __inline__ unsigned long get_msr(void) { unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); + __asm__ ("mfmsr %0" : "=r" (msr) :); return msr; } static __inline__ void set_msr(unsigned long msr) { - asm volatile("mtmsr %0" : : "r" (msr)); + __asm__ __volatile__("mtmsr %0" : : "r" (msr)); } /* ------------------------------------------------------------------------- */ ulong get_bus_freq (ulong ignore) { - /* measure the bus frequency using UART2 */ - /* 1st initilise it to run at 9600 - it takes approx 10*(1/9600) us to sens an 8N1 character at 9600bps - but due to chrystal inaccuracies on sandpoint we use 1145us */ - - int count=0, start, end; - int i; - volatile struct NS16550 *uart2; - - uart2=NS16550_init(1,115200/9600); - - - for (i =0; i< 10 ; i++) - { - NS16550_putc(uart2,0); /*send NUL*/ - start=mfspr(DEC); - NS16550_putc(uart2,0); /*send NUL*/ - end=mfspr(DEC); - count +=(start-end); - } - - count /=10; /*average number of decrements per char send*/ - count *=4; /*1 decrement per 4 bus cycles*/ - - /*time taken to do count cycles = 1145 us - therefore number of cycles per second is (1/(1145*10-6))*count - */ - return (1000000/1145)*count; + return 66666666; } /* ------------------------------------------------------------------------- */ @@ -84,30 +57,33 @@ ulong get_bus_freq (ulong ignore) * Measure CPU clock speed */ -/*table to convert pllratio to actual processor clock scaling factor (*10)*/ -/* if you are using a a different processor with your sandpoint, - have a look at pmc.c in the dink source for values, or - figure it out from the hardware book*/ +/* + * table to convert pllratio to actual processor clock scaling factor (*2) + * if you are using a a different processor with your sandpoint, + * have a look at pmc.c in the dink source for values, or + * figure it out from the hardware book + */ #ifdef CONFIG_MPC8240 -short pllratio_to_factor[] = { - 00, 00, 00, 10, 20, 20, 25, 00, 00, 00, 00, 00, 00, 00, 00, 00, - 00, 00, 00, 10, 00, 00, 00, 45, 30, 00, 40, 00, 00, 00, 35, 00, +const unsigned char pllratio_to_factor[32] = { + 0, 0, 0, 2, 4, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 2, 0, 0, 0, 9, 6, 0, 8, 0, 0, 0, 7, 0 }; +#else + #error Enter clock divider array here! #endif ulong get_gclk_freq (void) { uint hid1; - hid1=mfspr(HID1); + hid1 = mfspr(HID1); #ifdef CONFIG_MPC8240 - hid1=(hid1 >> (32-5)) & 0x1f; /* 5 bits for PLL ration on 8240*/ + hid1 = (hid1 >> (32-5)) & 0x1f; /* 5 bits for PLL ration on 8240*/ #else - hid1=(hid1 >> (32-4)) & 0xf; /* 4 bits on everythings else*/ + hid1 = (hid1 >> (32-4)) & 0xf; /* 4 bits on everythings else*/ #endif - return (pllratio_to_factor[hid1] * get_bus_freq(0))/10; - + return pllratio_to_factor[hid1] * get_bus_freq(0)/2; } /* ------------------------------------------------------------------------- */ diff --git a/common/Makefile b/common/Makefile index e0b8f10..d9df3bd 100644 --- a/common/Makefile +++ b/common/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk LIB = libcommon.a -ifneq ($(BOARD),cpci405) AOBJS = environment.o -endif COBJS = board.o main.o command.o \ cmd_boot.o cmd_bootm.o cmd_cache.o \ cmd_console.o cmd_date.o cmd_eeprom.o \ diff --git a/cpu/mpc8240/cpu.c b/cpu/mpc8240/cpu.c index 313653d..6ae70f4 100644 --- a/cpu/mpc8240/cpu.c +++ b/cpu/mpc8240/cpu.c @@ -34,9 +34,10 @@ int checkcpu(long clock) switch(version) { - case 0x0081: + case CPU_TYPE_8240: printf("MPC8240"); break; + default: return -1; /*not valid for this source*/ } @@ -155,10 +156,8 @@ mpc8240_mpc107_getreg(unsigned int regNum) } /* - * This procedure writes a 32-bit address MPC107 register, and returns - * a 32 bit value. It swaps the address to little endian before - * writing it to config address, and swaps the value to big endian - * before returning to the caller. + * This procedure writes a 32-bit address MPC107 register. It swaps + * the address to little endian before writing it to config address. */ void diff --git a/cpu/mpc8240/cpu_init.c b/cpu/mpc8240/cpu_init.c index 4234935..0120775 100644 --- a/cpu/mpc8240/cpu_init.c +++ b/cpu/mpc8240/cpu_init.c @@ -34,7 +34,8 @@ void cpu_init_f (void) { -#ifndef CONFIG_MOUSSE /* Mousse initialized in asm */ +/* MOUSSE and SANDPOINT boards initialized in asm */ +#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_SANDPOINT) register unsigned long val; CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); *//*reset PCISR*/ @@ -136,7 +137,7 @@ cpu_init_f (void) (CFG_BANK6_ENABLE << 6) | (CFG_BANK7_ENABLE << 7)); - //! Wait 200us before initialize other registers + /* ! Wait 200us before initialize other registers */ /*FIXME: write a decent udelay wait */ __asm__ __volatile__( " mtctr %0 \n \ @@ -148,7 +149,7 @@ cpu_init_f (void) CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); //set memory access going __asm__ __volatile__("eieio"); -#endif /* CONFIG_MOUSSE */ +#endif /* CONFIG_MOUSSE, CONFIG_SANDPOINT */ } diff --git a/cpu/mpc8240/start.S b/cpu/mpc8240/start.S index 071fa23..9c0ed09 100644 --- a/cpu/mpc8240/start.S +++ b/cpu/mpc8240/start.S @@ -56,7 +56,8 @@ /* We don't want the MMU yet. */ #undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ +/* FP, Machine Check and Recoverable Interr. */ +#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI ) /* * Set up GOT: Global Offset Table @@ -109,13 +110,14 @@ boot_warm: /* Initialize machine status; enable machine check interrupt */ /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ + li r3, MSR_KERNEL /* Set FP, ME, RI flags */ mtmsr r3 mtspr SRR1, r3 /* Make SRR1 match MSR */ - mfspr r3, ICR /* clear Interrupt Cause Register */ - addis r0,0,0x0000 /* lets make sure that r0 is really 0 */ + mtspr HID0, r0 /* disable I and D caches */ + + mfspr r3, ICR /* clear Interrupt Cause Register */ mfmsr r3 /* turn off address translation */ addis r4,0,0xffff @@ -141,6 +143,9 @@ boot_warm: #endif in_flash: +#if defined(CONFIG_SANDPOINT) + bl early_init_f /* must be ASM: no stack yet! */ +#endif /* * Setup BATs - cannot be done in C since we don't have a stack yet */ diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c index 5c35f47..5e2b511 100644 --- a/cpu/ppc4xx/405gp_enet.c +++ b/cpu/ppc4xx/405gp_enet.c @@ -277,8 +277,8 @@ int eth_init (bd_t *bis) for (i = 0; i < 1000; i++); out32 (EMAC_M0, in32 (EMAC_M0) & ~EMAC_M0_SRST); - speed = miiphy_speed(); - duplex = miiphy_duplex(); + speed = miiphy_speed(CONFIG_PHY_ADDR); + duplex = miiphy_duplex(CONFIG_PHY_ADDR); if (print_speed) { print_speed = 0; diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 232c91b..f2862ee 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -55,7 +55,7 @@ /* Dump out to the screen PHY regs */ /***********************************************************/ -void miiphy_dump(void) +void miiphy_dump(unsigned char addr) { unsigned long i; unsigned short data; @@ -63,7 +63,7 @@ void miiphy_dump(void) for(i=0; i<0x1A; i++) { - if(miiphy_read(0, i, &data)) + if(miiphy_read(addr, i, &data)) { printf("read error for reg %lx\n",i); return; @@ -104,7 +104,7 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value) sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; - sta_reg = sta_reg | (CONFIG_PHY_ADDR << 5); /* Phy address */ + sta_reg = sta_reg | (addr << 5); /* Phy address */ out32(EMAC_STACR, sta_reg); #if 0 /* test-only */ @@ -159,7 +159,7 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; - sta_reg = sta_reg | ((unsigned long)CONFIG_PHY_ADDR << 5); /* Phy address */ + sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */ memcpy(&sta_reg, &value,2); /* put in data */ out32(EMAC_STACR, sta_reg); @@ -182,43 +182,4 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) } /* phy_read */ -/***********************************************************/ -/* routine to read phy and determine the interface speed */ -/***********************************************************/ -int miiphy_speed() -{ - int speed = _10BASET; /* Assume 10Mbs */ - unsigned short bmcr = 0x0; - - if (miiphy_read(0,PHY_ANLPAR,&bmcr)) { - printf("phy speed1 read failed \n"); - miiphy_dump(); - } - - if ((bmcr & PHY_ANLPAR_100) != 0) { - speed = _100BASET; - } - - return (speed); -} -/***********************************************************/ -/* routine to read phy and determine the duplex mode */ -/***********************************************************/ -int miiphy_duplex() -{ - int speed = HALF; /* Assume HALF */ - unsigned short bmcr = 0x0; - - if (miiphy_read(0,PHY_ANLPAR,&bmcr)) - { - printf("phy duplex read failed \n"); - miiphy_dump(); - } - - if ((bmcr & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) - speed = FULL; - - return (speed); -} - #endif /* CONFIG_405GP */ diff --git a/include/config_AR405.h b/include/config_AR405.h index ceff179..5f7a367 100644 --- a/include/config_AR405.h +++ b/include/config_AR405.h @@ -61,6 +61,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS \ diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h index 0b8e755..4e5c119 100644 --- a/include/config_CPCI405.h +++ b/include/config_CPCI405.h @@ -60,6 +60,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ diff --git a/include/config_CPCIISER4.h b/include/config_CPCIISER4.h index 8606dc3..eb9d4f7 100644 --- a/include/config_CPCIISER4.h +++ b/include/config_CPCIISER4.h @@ -48,6 +48,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ diff --git a/include/config_CRAYL1.h b/include/config_CRAYL1.h index 001e4c8..eae105d 100644 --- a/include/config_CRAYL1.h +++ b/include/config_CRAYL1.h @@ -57,6 +57,7 @@ "L1cmd update; "\ "L1cmd boot" +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ diff --git a/include/config_CU824.h b/include/config_CU824.h index d0eda9f..1155b6f 100644 --- a/include/config_CU824.h +++ b/include/config_CU824.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -41,21 +41,20 @@ * (easy to change) */ -#define CONFIG_MPC8240 1 -#define CONFIG_CU824 1 +#define CONFIG_MPC8240 1 +#define CONFIG_CU824 1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTARGS " " -#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ +#define CONFIG_BOOTDELAY 5 -#define CONFIG_COMMANDS CONFIG_CMD_DFL +#define CONFIG_COMMANDS CONFIG_CMD_DFL /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -65,37 +64,37 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 8 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ +#define CFG_MAXARGS 8 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 #define CFG_RESET_ADDRESS 0xFFF00100 -#define CFG_EUMB_ADDR 0xFCE00000 +#define CFG_EUMB_ADDR 0xFCE00000 #define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ /* Maximum amount of RAM. */ @@ -131,38 +130,38 @@ #define CONFIG_SYS_CLK_FREQ 33000000 #define CFG_SERIAL_CLOCK (14745600 / 2) -#define CFG_HZ 1000 +#define CFG_HZ 1000 -#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 +#define CFG_ETH_DEV_FN 0x7800 +#define CFG_ETH_IOBASE 0x00104000 /* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 7 +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 /* Bit-field values for MCCR2. */ -#define CFG_REFINT 430 /* Refresh interval */ +#define CFG_REFINT 430 /* Refresh interval */ /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CFG_BSTOPRE 192 +#define CFG_BSTOPRE 192 /* Bit-field values for MCCR3. */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* Data latancy from read command */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* Data latancy from read command */ /* Bit-field values for MCCR4. */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 #define CFG_REGISTERD_TYPE_BUFFER 1 /* Memory bank settings. @@ -172,32 +171,32 @@ * address. Refer to the MPC8240 book. */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) #define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff #define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff #define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff #define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff #define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff #define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff #define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff #define CFG_BANK7_ENABLE 0 -#define CFG_ODCR 0xff +#define CFG_ODCR 0xff #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -225,23 +224,30 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ +#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /* Warining: environment is not EMBEDDED in the ppcboot code. * It's stored in flash separately. */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFF008000 -#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ +#define CFG_ENV_IS_IN_FLASH 1 +#if 0 +#define CFG_ENV_ADDR 0xFF008000 +#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ +#else +#define CFG_ENV_ADDR 0xFFFC0000 +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ +#endif /*----------------------------------------------------------------------- * Cache Configuration @@ -255,8 +261,8 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/config_ERIC.h b/include/config_ERIC.h index 06bc61e..6160504 100644 --- a/include/config_ERIC.h +++ b/include/config_ERIC.h @@ -89,6 +89,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ diff --git a/include/config_OCRTC.h b/include/config_OCRTC.h index a322f81..40679c4 100644 --- a/include/config_OCRTC.h +++ b/include/config_OCRTC.h @@ -48,6 +48,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ diff --git a/include/config_PIP405.h b/include/config_PIP405.h index b7b3ba4..64f654c 100644 --- a/include/config_PIP405.h +++ b/include/config_PIP405.h @@ -231,6 +231,7 @@ /************************************************************ * Ethernet Stuff ***********************************************************/ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ /************************************************************ diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h index a70b5cb..eced9fd 100644 --- a/include/config_Sandpoint8240.h +++ b/include/config_Sandpoint8240.h @@ -10,6 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H + /* * High Level Configuration Options * (easy to change) @@ -17,13 +18,12 @@ #define CONFIG_MPC8240 1 #define CONFIG_SANDPOINT 1 +#define USE_DINK32 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#undef CONFIG_BOOTARGS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_DRAM_SPEED 100 /* MHz */ +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ +#define CONFIG_BOOTARGS " " #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) @@ -34,57 +34,61 @@ /* * Miscellaneous configurable options */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 8 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_SIZE ((uint)(512 * 1024)) /* sandpoint has tiny eeprom */ - -#ifdef DEBUG - #define CFG_MONITOR_BASE CFG_SDRAM_BASE +#define CFG_SDRAM_BASE 0x00000000 + +#if defined (USE_DINK32) + #define CFG_MONITOR_LEN 0x00020000 + #define CFG_MONITOR_BASE 0x00090000 + #define CFG_RAMBOOT 1 + #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_INIT_RAM_END (CFG_INIT_RAM_ADDR + 0x10000) /* End of used area in DPRAM */ + #define CFG_INIT_DATA_SIZE 256 /* size in bytes reserved for initial data */ + #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) + #define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET #else - #define CFG_MONITOR_BASE CFG_FLASH_BASE + #undef CFG_RAMBOOT #endif -#ifdef DEBUG -#define CFG_MONITOR_LEN (4 <<20) /* if we're running in ram, give us plenty of space for debug info*/ -#else -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00008000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00004000 /* Total Size of Environment Sector */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CFG_EUMB_ADDR 0xFC000000 +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 +#define CFG_EUMB_ADDR 0xFC000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash*/ +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x01000000 +#define FLASH_BASE0_PRELIM 0xFFF80000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash*/ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET #define CFG_WINBOND_83C553 1 /*has a winbond bridge */ @@ -103,19 +107,20 @@ */ -#define CFG_ROMNAL 8 /*rom/flash next access time*/ -#define CFG_ROMFAL 16 /*rom/flash access time*/ +#define CFG_ROMNAL 7 /*rom/flash next access time*/ +#define CFG_ROMFAL 11 /*rom/flash access time*/ -#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles*/ +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles*/ /* the following are for SDRAM only*/ -#define CFG_BSTOPRE 604 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latancy from read command*/ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ #define CFG_REGISTERD_TYPE_BUFFER 1 @@ -124,77 +129,53 @@ the upper two bits will be 0, and the lower 20 bits will be set to 0x00000 for a start address, or 0xfffff for an end address*/ -#define CFG_BANK0_START 0x00000000 - -#define CFG_BANK0_END 0x01ffffff -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x01000000 -#define CFG_BANK1_END 0x00ffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x02000000 -#define CFG_BANK2_END 0x02ffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x03000000 -#define CFG_BANK3_END 0x03ffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x04000000 -#define CFG_BANK4_END 0x04ffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x05000000 -#define CFG_BANK5_END 0x05ffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x06000000 -#define CFG_BANK6_END 0x06ffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x07000000 -#define CFG_BANK7_END 0x07ffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff /* configures line driver impedances, - see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory - see 8240 book for details*/ -#define CFG_IBAT0L FLASH_BASE0_PRELIM | BATL_CACHEINHIBIT | BATL_PP_10 -#define CFG_IBAT0U FLASH_BASE0_PRELIM | BATU_BL_16M | BATU_VS | BATU_VP -#define CFG_IBAT1L 0x00000000 | BATL_CACHEINHIBIT | BATL_PP_10 -#define CFG_IBAT1U 0x00000000 | BATU_BL_128M | BATU_VS | BATU_VP -#define CFG_IBAT2L CFG_ISA_MEM | BATL_MEMCOHERENCE | BATL_PP_10 -#define CFG_IBAT2U CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP -#define CFG_IBAT3L CFG_ISA_IO | BATL_MEMCOHERENCE | BATL_PP_10 -#define CFG_IBAT3U CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP -#define CFG_DBAT0L FLASH_BASE0_PRELIM | BATL_MEMCOHERENCE | BATL_WRITETHROUGH | BATL_PP_10 -#define CFG_DBAT0U FLASH_BASE0_PRELIM | BATU_BL_16M | BATU_VS | BATU_VP -#define CFG_DBAT1L 0x00000000 | BATL_MEMCOHERENCE | BATL_WRITETHROUGH | BATL_PP_10 -#define CFG_DBAT1U 0x00000000 | BATU_BL_128M | BATU_VS | BATU_VP -#define CFG_DBAT2L CFG_ISA_MEM | BATL_MEMCOHERENCE | BATL_PP_10 -#define CFG_DBAT2U CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP -#define CFG_DBAT3L CFG_ISA_IO | BATL_MEMCOHERENCE | BATL_PP_10 -#define CFG_DBAT3U CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END 0x03ffffff +#define CFG_BANK1_START 0x04000000 +#define CFG_BANK1_END 0x07ffffff +#define CFG_BANK2_START 0x08000000 +#define CFG_BANK2_END 0x0bffffff +#define CFG_BANK3_START 0x0c000000 +#define CFG_BANK3_END 0x0fffffff +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 + +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 +#define CFG_ODCR 0xff /* configures line driver impedances, + see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the currently accessed page in memory + see 8240 book for details*/ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ @@ -213,7 +194,7 @@ #define CONFIG_SDRAM_50MHZ #undef NR_8259_INTS -#define NR_8259_INTS 1 +#define NR_8259_INTS 1 #define CONFIG_DISK_SPINUP_TIME 1000000 diff --git a/include/config_WALNUT405.h b/include/config_WALNUT405.h index 4b4f062..569a883 100644 --- a/include/config_WALNUT405.h +++ b/include/config_WALNUT405.h @@ -78,6 +78,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ diff --git a/include/mpc8240.h b/include/mpc8240.h index 40e7dfa..2500617 100755 --- a/include/mpc8240.h +++ b/include/mpc8240.h @@ -138,10 +138,10 @@ #define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW) -/*macros to wite to conif registers. addr should be a constant in all cases */ +/* Macros to write to config registers. addr should be a constant in all cases */ #define CONFIG_WRITE_BYTE( addr, data ) \ - __asm__ ( \ + __asm__ __volatile__( \ " stwbrx %1, 0, %0\n \ sync\n \ stb %3, %4(%2)\n \ @@ -152,10 +152,10 @@ "n" ((addr) & 3)); #define CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ ( \ + __asm__ __volatile__( \ " stwbrx %1, 0, %0\n \ sync\n \ - stwbrx %3, %4, %2\n \ + sthbrx %3, %4, %2\n \ sync " \ : /* no output */ \ : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ @@ -164,7 +164,7 @@ /* this assumes it's writeing on word boundaries*/ #define CONFIG_WRITE_WORD( addr, data ) \ - __asm__ ( \ + __asm__ __volatile__( \ " stwbrx %1, 0, %0\n \ sync\n \ stwbrx %3, 0, %2\n \ @@ -175,7 +175,7 @@ /* Configuration register reads*/ -#define CONFIG_READ_BYTE( addr , reg ) \ +#define CONFIG_READ_BYTE( addr, reg ) \ __asm__ ( \ " stwbrx %1, 0, %2\n \ sync\n \ @@ -186,7 +186,7 @@ "r" (CONFIG_DATA), "n" ((addr) & 3)); -#define CONFIG_READ_HALFWORD( addr , reg ) \ +#define CONFIG_READ_HALFWORD( addr, reg ) \ __asm__ ( \ " stwbrx %1, 0, %2\n \ sync\n \ @@ -198,7 +198,7 @@ "r" ((addr) & 3)); /* this assumes it's reading on word boundaries*/ -#define CONFIG_READ_WORD( addr , reg ) \ +#define CONFIG_READ_WORD( addr, reg ) \ __asm__ ( \ " stwbrx %1, 0, %2\n \ sync\n \ @@ -266,7 +266,7 @@ #define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */ #define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */ -/* some values for soem of the above */ +/* some values for some of the above */ #define PICR1_CF_APARK 0x00000008 #define PICR1_LE_MODE 0x00000020 @@ -354,7 +354,7 @@ #define MCCR4_SDMODE_SHIFT 8 #define MCCR4_ACTTORW_MSK 0x000000f0 #define MCCR4_ACTTORW_SHIFT 4 -#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[0-1]*/ +#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/ #define MCCR4_BSTOPRE6TO9_SHIFT 0 #define MICR_ADDR_MASK 0x0ff00000 diff --git a/include/ppcboot.h b/include/ppcboot.h index f4e1af0..8bf9eb6 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -151,6 +151,9 @@ typedef struct init_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_SANDPOINT) + void * console_addr; +#endif } init_data_t; /*