From: wdenk Date: Wed, 18 Oct 2000 13:18:52 +0000 (+0000) Subject: Tested (and fixed) FPS850L configuration; added ethernet support for X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=46568a64b79cd90d868d25b11ebb9c75b55fc426;p=users%2Frw%2Fppcboot.git Tested (and fixed) FPS850L configuration; added ethernet support for FADS860T. Some small fixes in the docs. --- diff --git a/CHANGELOG b/CHANGELOG index 93fb0ea..db86741 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -54,6 +54,14 @@ Open Issues: Fix Exception handling for "Software Emulation Exception" etc. +====================================================================== +Modifications since 0.5.3: +====================================================================== + +* Tested (and fixed) FPS850L configuration + +* Added ethernet support for FADS860T (thanks to Christian Vejlbo) + ====================================================================== Modifications for 0.5.3: ====================================================================== @@ -68,7 +76,7 @@ Modifications for 0.5.3: * Added ';' as command separator for the default boot command: now "bootcmd" can contain a sequence of several commands which are executed in sequence. Please note that there is absolutely no flow - control, conditional execition, or the like: PPCBoot will always + control, conditional execution, or the like: PPCBoot will always run all commands strictly one after the other [assuming the command returns to PPCBoot, which cannot be expected for instance when you start an OS kernel...] diff --git a/CREDITS b/CREDITS index 978f007..9c2a149 100644 --- a/CREDITS +++ b/CREDITS @@ -66,3 +66,7 @@ D: Author of LiMon-1.4.2, which contributed some ideas N: Paolo Scaffardi E: arsenio@tin.it D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard + +N: Christian Vejlbo +E: christian.vejlbo@tellabs.com +D: FADS860T ethernet support diff --git a/Makefile b/Makefile index 04c8b38..8aba8b5 100644 --- a/Makefile +++ b/Makefile @@ -101,6 +101,7 @@ unconfig: TQM823L_config \ TQM850L_config \ +FPS850L_config \ TQM855L_config \ TQM860L_config : unconfig @echo "Configuring for $(@:_config=) Board..." ; \ diff --git a/README b/README index c4522fd..b4b0e2c 100644 --- a/README +++ b/README @@ -139,11 +139,10 @@ The following options need to be configured: CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L, CONFIG_TQM860L, CONFIG_ETX094, CONFIG_ADCIOP, CONFIG_CPCI405, CONFIG_COGENT, CONFIG_FADS, - CONFIG_SPD823TS + CONFIG_SPD823TS,CONFIG_FPS850L --- FIXME --- not tested yet: - CONFIG_TQM860, CONFIG_FPS850L, CONFIG_MBX, - CONFIG_ADS, CONFIG_RPXLITE, - CONFIG_RPXCLASSIC, CONFIG_BSEIP + CONFIG_TQM860, CONFIG_MBX, CONFIG_ADS, + CONFIG_RPXLITE, CONFIG_RPXCLASSIC, CONFIG_BSEIP - Console Interface: @@ -366,9 +365,9 @@ PPCBoot is intended to be simple to build. After installing the sources you must configure PPCBoot for one specific board type. This is done by typing: - make config_name + make NAME_config -where "config_name" is the name of one of the existing +where "NAME_config" is the name of one of the existing configurations; the following names are suported: TQM823L_config diff --git a/include/commproc.h b/include/commproc.h index 4a0cd66..5e265b7 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -490,6 +490,38 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ #endif /* CONFIG_FADS850SAR */ +/*** FADS860T********************************************************/ + +#if defined(CONFIG_MPC860T) && defined(CONFIG_FADS) +/* This ENET stuff is for the MPC860TFADS with ethernet on SCC1. + */ + +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) + +#define PB_ENET_TENA ((uint)0x00001000) + +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002c) + +/* 68160 PHY control */ + +#define PC_ENET_ETHLOOP ((ushort)0x0800) +#define PC_ENET_TPFLDL ((ushort)0x0400) +#define PC_ENET_TPSQEL ((ushort)0x0200) + +#endif /* CONFIG_FADS860T */ + + /*** BSEIP **********************************************************/ #ifdef CONFIG_BSEIP @@ -567,7 +599,7 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_ETX094 */ -/*** FPC850 *********************************************************/ +/*** FPS850L *********************************************************/ #ifdef CONFIG_FPS850L /* Bits in parallel I/O port registers that have to be set/cleared @@ -592,7 +624,7 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_FPS850L */ -/*** TQM860L, TQM855L*************************************************/ +/*** TQM860L, TQM855L ************************************************/ #if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L)) /* Bits in parallel I/O port registers that have to be set/cleared diff --git a/include/config_FADS860T.h b/include/config_FADS860T.h index 3d11571..9e80813 100644 --- a/include/config_FADS860T.h +++ b/include/config_FADS860T.h @@ -63,15 +63,13 @@ #define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ #define CONFIG_BOOTCOMMAND "bootm 2800100" /* autoboot command */ -#define CONFIG_BOOTARGS " " - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) /* no network yet ??? */ +#define CONFIG_BOOTARGS "" /* * Miscellaneous configurable options */ #undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -189,7 +187,8 @@ *----------------------------------------------------------------------- * set the PLL, the low-power modes and the reset control (15-29) */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -222,7 +221,7 @@ */ /* the other CS:s are determined by looking at parameters in BCSRx */ -#define BCSR_ADDR ((uint) 0x2100000) +#define BCSR_ADDR ((uint) 0xFF01000) #define BCSR_SIZE ((uint)(64 * 1024)) #define FLASH_BASE0_PRELIM 0x2800000 /* FLASH bank #0 */ diff --git a/include/config_FPS850L.h b/include/config_FPS850L.h new file mode 100644 index 0000000..58b9549 --- /dev/null +++ b/include/config_FPS850L.h @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#define CONFIG_BAUDRATE 115200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/LinuxPPC " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_TFTP_LOADADDR 0x100000 /* default load address */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) + +/*----------------------------------------------------------------------- + * SUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/config_SPD823TS.h b/include/config_SPD823TS.h index 2480577..6495096 100644 --- a/include/config_SPD823TS.h +++ b/include/config_SPD823TS.h @@ -60,6 +60,8 @@ #define CONFIG_ETHADDR 00:d0:93:00:01:cb #define CONFIG_IPADDR 10.0.0.98 #define CONFIG_SERVERIP 10.0.0.1 +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" /*----------------------------------------------------------------------*/ /* diff --git a/mpc8xx/cpu_init.c b/mpc8xx/cpu_init.c index 7d91ff5..2ded683 100644 --- a/mpc8xx/cpu_init.c +++ b/mpc8xx/cpu_init.c @@ -100,7 +100,7 @@ cpu_init_f (volatile immap_t *immr) * has been determined */ -#if defined(CONFIG_SPD823TS) +#if defined(CONFIG_SPD823TS) || (defined(CONFIG_MPC860T) && defined(CONFIG_FADS)) /* XXX - FIXME - XXX * I still don't understand why some systems work only with this * statement here, and others work only without it. diff --git a/mpc8xx/scc.c b/mpc8xx/scc.c index e58b1af..970e445 100644 --- a/mpc8xx/scc.c +++ b/mpc8xx/scc.c @@ -177,7 +177,7 @@ int eth_init(bd_t *bis) volatile immap_t *immr = (immap_t *)CFG_IMMR; -#if defined(CONFIG_FADS) +#if defined(CONFIG_FADS) && !defined(CONFIG_MPC860T) *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN); *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE; *((uint *) BCSR1) &= ~BCSR1_ETHEN; @@ -393,6 +393,18 @@ int eth_init(bd_t *bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif +#if defined(CONFIG_FADS) && defined(CONFIG_MPC860T) + /* + * Port C is used to control the PHY,MC68160. + */ + immr->im_ioport.iop_pcdir |= + (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); + + immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; + immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif /* FADS860T */ + /* * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive */