From: Marc Zyngier <maz@kernel.org>
Date: Fri, 17 Jan 2025 11:06:33 +0000 (+0000)
Subject: Merge branch kvm-arm64/nv-resx-fixes-6.14 into kvmarm-master/next
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=3643b334aa8f02ddcedc093d7de623378192da06;p=users%2Fdwmw2%2Flinux.git

Merge branch kvm-arm64/nv-resx-fixes-6.14 into kvmarm-master/next

* kvm-arm64/nv-resx-fixes-6.14:
  : .
  : Fixes for NV sysreg accessors. From the cover letter:
  :
  : "Joey recently reported that some rather basic tests were failing on
  : NV, and managed to track it down to critical register fields (such as
  : HCR_EL2.E2H) not having their expect value.
  :
  : Further investigation has outlined a couple of critical issues:
  :
  : - Evaluating HCR_EL2.E2H must always be done with a sanitising
  :   accessor, no ifs, no buts. Given that KVM assumes a fixed value for
  :   this bit, we cannot leave it to the guest to mess with.
  :
  : - Resetting the sysreg file must result in the RESx bits taking
  :   effect. Otherwise, we may end-up making the wrong decision (see
  :   above), and we definitely expose invalid values to the guest. Note
  :   that because we compute the RESx masks very late in the VM setup, we
  :   need to apply these masks at that particular point as well.
  : [...]"
  : .
  KVM: arm64: nv: Apply RESx settings to sysreg reset values
  KVM: arm64: nv: Always evaluate HCR_EL2 using sanitising accessors

Signed-off-by: Marc Zyngier <maz@kernel.org>

# Conflicts:
#	arch/arm64/kvm/nested.c
---

3643b334aa8f02ddcedc093d7de623378192da06
diff --cc arch/arm64/kvm/nested.c
index 9895372fb3b6a,dd6480cf90ea5..f73eb79f61165
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@@ -1271,21 -1272,10 +1272,25 @@@ int kvm_init_nv_sysregs(struct kvm_vcp
  		res0 |= MDCR_EL2_EnSTEPOP;
  	set_sysreg_masks(kvm, MDCR_EL2, res0, res1);
  
 +	/* CNTHCTL_EL2 */
 +	res0 = GENMASK(63, 20);
 +	res1 = 0;
 +	if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RME, IMP))
 +		res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK;
 +	if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, CNTPOFF)) {
 +		res0 |= CNTHCTL_ECV;
 +		if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, IMP))
 +			res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT |
 +				 CNTHCTL_EL1NVPCT | CNTHCTL_EL1NVVCT);
 +	}
 +	if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP))
 +		res0 |= GENMASK(11, 8);
 +	set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1);
 +
+ out:
+ 	for (enum vcpu_sysreg sr = __SANITISED_REG_START__; sr < NR_SYS_REGS; sr++)
+ 		(void)__vcpu_sys_reg(vcpu, sr);
+ 
  	return 0;
  }