From: Joerg Roedel <jroedel@suse.de>
Date: Mon, 1 Jul 2019 12:41:24 +0000 (+0200)
Subject: Merge branch 'arm/renesas' into arm/smmu
X-Git-Tag: v5.3-rc1~172^2^3~2
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=3430abd6f403ce43375266798a8571646d15b5cd;p=linux.git

Merge branch 'arm/renesas' into arm/smmu
---

3430abd6f403ce43375266798a8571646d15b5cd
diff --cc drivers/iommu/ipmmu-vmsa.c
index 12bcb95bdaa8,408ad0b25919..ad0098c0c87c
--- a/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@@ -495,7 -459,54 +459,55 @@@ static void ipmmu_domain_setup_context(
  	 */
  	ipmmu_ctx_write_all(domain, IMCTR,
  			    IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
+ }
+ 
+ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ {
+ 	int ret;
+ 
+ 	/*
+ 	 * Allocate the page table operations.
+ 	 *
+ 	 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
+ 	 * access, Long-descriptor format" that the NStable bit being set in a
+ 	 * table descriptor will result in the NStable and NS bits of all child
+ 	 * entries being ignored and considered as being set. The IPMMU seems
+ 	 * not to comply with this, as it generates a secure access page fault
+ 	 * if any of the NStable and NS bits isn't set when running in
+ 	 * non-secure mode.
+ 	 */
+ 	domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
+ 	domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
+ 	domain->cfg.ias = 32;
+ 	domain->cfg.oas = 40;
+ 	domain->cfg.tlb = &ipmmu_gather_ops;
+ 	domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
+ 	domain->io_domain.geometry.force_aperture = true;
+ 	/*
+ 	 * TODO: Add support for coherent walk through CCI with DVM and remove
+ 	 * cache handling. For now, delegate it to the io-pgtable code.
+ 	 */
++	domain->cfg.coherent_walk = false;
+ 	domain->cfg.iommu_dev = domain->mmu->root->dev;
+ 
+ 	/*
+ 	 * Find an unused context.
+ 	 */
+ 	ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
+ 	if (ret < 0)
+ 		return ret;
+ 
+ 	domain->context_id = ret;
+ 
+ 	domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
+ 					   domain);
+ 	if (!domain->iop) {
+ 		ipmmu_domain_free_context(domain->mmu->root,
+ 					  domain->context_id);
+ 		return -EINVAL;
+ 	}
  
+ 	ipmmu_domain_setup_context(domain);
  	return 0;
  }