From: AngeloGioacchino Del Regno Date: Mon, 22 May 2023 09:30:01 +0000 (+0200) Subject: arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=33518b51f95c10a00edf5deb8901a808a6eaba0a;p=users%2Fwilly%2Fpagecache.git arm64: dts: mediatek: mt8192: Make sure MSDCPLL's rate is 400MHz Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have seen is this clock being set at around 384MHz. This is a performance concern (and possibly a stability one, for picky eMMC/SD cards) as the MSDC controller's internal divier will choose a frequency that is lower than expected, in the end causing a difference in the expected mmc/sd device's timings. Make sure that the MSDCPLL frequency is always set to 400MHz to both improve performance and reliability of the sd/mmc storage. Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230522093002.75137-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index faaff39155dca..65bc8b4046211 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -679,6 +679,8 @@ compatible = "mediatek,mt8192-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; + assigned-clock-rates = <400000000>; }; systimer: timer@10017000 {