From: wdenk Date: Mon, 18 Feb 2002 00:45:52 +0000 (+0000) Subject: Patch by Nye Liu 31 Jan 2002 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=31d866fb0e5383507a3f5c9d68aa29f8ea15b460;p=users%2Frw%2Fppcboot.git Patch by Nye Liu 31 Jan 2002 - add extra cache management functionality - add more 750CX pvid detection - fix cpu/74xx_7xx/speed.c - added a few 'sync's to cpu/74xx_7xx/start.S (just to make GDB happy? -wd) --- diff --git a/CHANGELOG b/CHANGELOG index b158853..9d620d0 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,15 @@ Modifications for 1.1.5: ====================================================================== +* Patch by Nye Liu 31 Jan 2002 + - add extra cache management functionality + - add more 750CX pvid detection + - fix cpu/74xx_7xx/speed.c + - added a few 'sync's to cpu/74xx_7xx/start.S + (just to make GDB happy? -wd) + +* Remove obsolete board/sandpoint/interrupts* files + * Fix flash code for PCIPPC2/PCIPPC6 boards (cannot use unlock bypas mode on Am29F040B) diff --git a/Makefile b/Makefile index 81367d8..c4fab7b 100644 --- a/Makefile +++ b/Makefile @@ -35,7 +35,7 @@ ifndef CROSS_COMPILE ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else -CROSS_COMPILE = ppc_82xx- +CROSS_COMPILE = powerpc-$(HOSTOS)- endif endif diff --git a/board/etx094/flash.c b/board/etx094/flash.c index 1aab41d..65ef31f 100644 --- a/board/etx094/flash.c +++ b/board/etx094/flash.c @@ -450,11 +450,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - #ifdef CONFIG_FLASH_16BIT + s_addr = (volatile unsigned short *)(info->start[0]); *s_addr = 0x00F0; /* reset bank */ #else + addr = (volatile unsigned long *)info->start[0]; *addr = 0x00F000F0; /* reset bank */ #endif diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index 104ce4d..e37846a 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -36,8 +36,19 @@ Skeleton NIC driver for Etherboot #undef DEBUG /* Restart autoneg if we detect link is up on phy init. */ -/* (fixes some autoneg problems with bad hubs/switches) */ -#undef RESTART_AUTONEG + +/* + * The GT doc's say that after Rst is deasserted, and the PHY + * reports autoneg compleate, it runs through its autoneg + * procedures. This doesn't seem to be the case for MII + * PHY's. To work around this check for link up && autoneg + * compleate when initilizing the port. If they are both set, + * then restart PHY autoneg. Of course, it may be something + * compleatly different. + */ +#ifdef CONFIG_ETHER_PORT_MII +# define RESTART_AUTONEG +#endif /* do this if you want to filter for our mac */ #define USE_MAC_HASH_TABLE @@ -107,19 +118,22 @@ static void evb64260_handle_SMI(unsigned int icr) #endif if(icr&0x10000000) { - unsigned short mii_11; unsigned int psr; - mii_11=miiphy_read_ret(ETHER_PORT_PHY,0x11); psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF); #ifdef DEBUG printf("PHY state change:\n" - " GT:%s:%s:%s:%s\n" - "mii:%s:%s:%s:%s %s:%s %s\n", + " GT:%s:%s:%s:%s\n" psr&1?"100":" 10", psr&8?" Link":"nLink", psr&2?"FD":"HD", - psr&4?" FC":"nFC", + psr&4?" FC":"nFC"); +#ifdef ZUMA_NTL /* non-standard mii reg (intel lxt972a) */ + { + unsigned short mii_11; + mii_11=miiphy_read_ret(ETHER_PORT_PHY,0x11); + + printf(" mii:%s:%s:%s:%s %s:%s %s\n", mii_11&(1<<14)?"100":" 10", mii_11&(1<<10)?" Link":"nLink", mii_11&(1<<9)?"FD":"HD", @@ -129,7 +143,9 @@ static void evb64260_handle_SMI(unsigned int icr) mii_11&(1<<8)?"AN":"Manual", "" ); -#endif + } +#endif /* ZUMA_NTL */ +#endif /* DEBUG */ } } @@ -377,6 +393,52 @@ evb64260_dump_mii(bd_t *bis, unsigned short phy) } #endif +#ifdef RESTART_AUTONEG + +/* If link is up && autoneg compleate, and if + * GT and PHY disagree about link capabilitys, + * restart autoneg - something screwy with FD/HD + * unless we do this. */ +static void +check_phy_state(void) +{ + int bmsr = miiphy_read_ret(ETHER_PORT_PHY, PHY_BMSR); + int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF); + + if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { + int nego = miiphy_read_ret(ETHER_PORT_PHY, PHY_ANAR) & + miiphy_read_ret(ETHER_PORT_PHY, PHY_ANLPAR); + int want; + + if (nego & PHY_ANLPAR_TXFD) { + want = 0x3; + printf("MII: 100Base-TX, Full Duplex\n"); + } else if (nego & PHY_ANLPAR_TX) { + want = 0x1; + printf("MII: 100Base-TX, Half Duplex\n"); + } else if (nego & PHY_ANLPAR_10FD) { + want = 0x2; + printf("MII: 10Base-T, Full Duplex\n"); + } else if (nego & PHY_ANLPAR_10) { + want = 0x0; + printf("MII: 10Base-T, Half Duplex\n"); + } else { + printf("MII: Unknown link-foo! %x\n", nego); + return; + } + + if ((psr & 0x3) != want) { + printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", + psr & 0x3, want); + miiphy_write(ETHER_PORT_PHY,0, + miiphy_read_ret(ETHER_PORT_PHY,0) | (1<<9)); + udelay(10000); /* the EVB's GT takes a while to notice phy + went down and up */ + } + } +} +#endif + /************************************************************************** PROBE - Look for an adapter, this routine's visible to the outside ***************************************************************************/ @@ -480,14 +542,7 @@ evb64260_eth0_probe(bd_t *bis) /* 2400 */ #ifdef RESTART_AUTONEG - /* if link is up, restart PHY autoneg - something screwy with FD/HD - * unless we do this */ - if(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF) & 8) { - miiphy_write(ETHER_PORT_PHY,0, - miiphy_read_ret(ETHER_PORT_PHY,0) | (1<<9)); - udelay(10000); /* the EVB's GT takes a while to notice phy - went down and up */ - } + check_phy_state(); #endif printf("Waiting for link up..\n"); diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c index dabc3a9..636e04e 100644 --- a/board/evb64260/flash.c +++ b/board/evb64260/flash.c @@ -33,7 +33,11 @@ #include #include "intel_flash.h" -#undef DEBUG +#define FLASH_ROM 0xFFFD /* unknown flash type */ +#define FLASH_RAM 0xFFFE /* unknown flash type */ +#define FLASH_MAN_UNKNOWN 0xFFFF0000 + +/* #define DEBUG */ /* Intel flash commands */ int flash_erase_intel(flash_info_t *info, int s_first, int s_last); @@ -432,14 +436,14 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) info->flash_id += FLASH_28F640J3A; info->sector_count = 64; info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ - if(info->width==4) info->size*=2; /* 2x16 */ + if(fl_width==4) info->size*=2; /* 2x16 */ break; case INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ - if(info->width==4) info->size*=2; /* 2x16 */ + if(fl_width==4) info->size*=2; /* 2x16 */ break; default: @@ -486,9 +490,9 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) caddr = (volatile unsigned char *)(info->start[i]); saddr = (volatile unsigned short *)(info->start[i]); laddr = (volatile unsigned long *)(info->start[i]); - if(info->width==1) + if(fl_width==1) info->protect[i] = caddr[2] & 1; - else if(info->width==2) + else if(fl_width==2) info->protect[i] = saddr[2] & 1; else info->protect[i] = laddr[2] & 1; @@ -506,6 +510,7 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info) return (info->size); } +/* TODO: 2x16 unsupported */ int flash_erase (flash_info_t *info, int s_first, int s_last) { @@ -513,6 +518,9 @@ flash_erase (flash_info_t *info, int s_first, int s_last) int flag, prot, sect, l_sect; ulong start, now, last; + /* TODO: 2x16 unsupported */ + if(info->width==4) return 1; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { for (sect = s_first; sect<=s_last; sect++) { diff --git a/board/evb64260/local.h b/board/evb64260/local.h new file mode 100644 index 0000000..32d74be --- /dev/null +++ b/board/evb64260/local.h @@ -0,0 +1,58 @@ +/* + * include/local.h - local configuration options, board specific + */ + +#ifndef __LOCAL_H +#define __LOCAL_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* This tells PPCBoot that the config options are compiled in */ +/* #undef ENV_IS_EMBEDDED */ +/* Don't touch this! PPCBOOT figures this out based on other + * magic. */ + +/* Uncomment and define any of the below options */ + +/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ + +/* These want string arguments */ +/* #define CONFIG_BOOTARGS */ +/* #define CONFIG_BOOTCOMMAND */ +/* #define CONFIG_RAMBOOTCOMMAND */ +/* #define CONFIG_NFSBOOTCOMMAND */ +/* #define CFG_AUTOLOAD */ +/* #define CONFIG_PREBOOT */ + +/* These don't */ + +/* #define CONFIG_BOOTDELAY */ +/* #define CONFIG_BAUDRATE */ +/* #define CONFIG_LOADS_ECHO */ +/* #define CONFIG_ETHADDR */ +/* #define CONFIG_ETH2ADDR */ +/* #define CONFIG_ETH3ADDR */ +/* #define CONFIG_IPADDR */ +/* #define CONFIG_SERVERIP */ +/* #define CONFIG_ROOTPATH */ +/* #define CONFIG_GATEWAYIP */ +/* #define CONFIG_NETMASK */ +/* #define CONFIG_HOSTNAME */ +/* #define CONFIG_BOOTFILE */ +/* #define CONFIG_LOADADDR */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +#define CONFIG_ETHADDR 00:11:22:33:44:55 + +/* next two ethernet hwaddrs */ +#define CONFIG_ETH1ADDR 00:11:22:33:44:66 +#define CONFIG_ETH2ADDR 00:11:22:33:44:77 + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c index c9cc5a2..c87046d 100644 --- a/board/evb64260/zuma_pbb.c +++ b/board/evb64260/zuma_pbb.c @@ -1,5 +1,11 @@ #include #include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#include +#include +#endif + #include #include "zuma_pbb.h" @@ -146,3 +152,37 @@ void zuma_init_pbb(void) zuma_pbb_reg->timestamp); } + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +static int last_cmd=4; /* write increment */ +static int last_size=64; + +int +do_zuma_init_pbb(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + zuma_init_pbb(); + return 0; +} + +int +do_zuma_test_dma(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + if(argc>1) { + last_cmd=simple_strtoul(argv[1],NULL,10); + } + if(argc>2) { + last_size=simple_strtoul(argv[2],NULL,10); + } + zuma_test_dma(last_cmd,last_size); + return 0; +} + +int +do_zuma_init_mbox(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + zuma_mbox_init(); + return 0; +} + +#endif /* CFG_CMD_BSP */ diff --git a/board/sandpoint/interrupts.c b/board/sandpoint/interrupts.c deleted file mode 100644 index b35bb9a..0000000 --- a/board/sandpoint/interrupts.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -/****************************************************************************/ - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long get_dec(void) -{ - unsigned long val; - - asm volatile("mfdec %0" : "=r" (val) :); - return val; -} - - -static __inline__ void set_dec(unsigned long val) -{ - asm volatile("mtdec %0" : : "r" (val)); -} - - -void enable_interrupts (void) -{ - set_msr (get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int disable_interrupts (void) -{ - ulong msr = get_msr(); - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -/****************************************************************************/ - -void -interrupt_init (bd_t *bd) -{ - - set_msr (get_msr() | MSR_EE); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt(struct pt_regs *regs) -{ - -} - -/****************************************************************************/ - -/* - * blank int handlers. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ -} - -void -irq_free_handler(int vec) -{ - -} - -/*TODO: some handlers for winbond and 87308 interrupts - and what about generic pci inteerupts? - vga? - */ - -volatile ulong timestamp = 0; - -void timer_interrupt(struct pt_regs *regs) -{ - timestamp++; -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} diff --git a/board/sandpoint/interrupts.h b/board/sandpoint/interrupts.h deleted file mode 100644 index 316d04c..0000000 --- a/board/sandpoint/interrupts.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _INTERRUPTS_H_ -#define _INTERRUPTS_H_ - -void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg); - -void irq_free_handler(int vec); - -#endif diff --git a/cpu/74xx_7xx/Makefile b/cpu/74xx_7xx/Makefile index f913c6d..0e10d3a 100644 --- a/cpu/74xx_7xx/Makefile +++ b/cpu/74xx_7xx/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -ASOBJS = kgdb.o io.o +ASOBJS = cache.o kgdb.o io.o OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S new file mode 100644 index 0000000..9cadc16 --- /dev/null +++ b/cpu/74xx_7xx/cache.S @@ -0,0 +1,381 @@ +#include +#include +#include "version.h" + +#include +#include + +#include +#include + +#ifndef CACHE_LINE_SIZE +# define CACHE_LINE_SIZE L1_CACHE_BYTES +#endif + +#if CACHE_LINE_SIZE == 128 +#define LG_CACHE_LINE_SIZE 7 +#elif CACHE_LINE_SIZE == 32 +#define LG_CACHE_LINE_SIZE 5 +#elif CACHE_LINE_SIZE == 16 +#define LG_CACHE_LINE_SIZE 4 +#elif CACHE_LINE_SIZE == 8 +#define LG_CACHE_LINE_SIZE 3 +#else +# error "Invalid cache line size!" +#endif + +/* + * Invalidate L1 instruction cache. + */ +_GLOBAL(invalidate_l1_instruction_cache) + mfspr r3,PVR + rlwinm r3,r3,16,16,31 + cmpi 0,r3,1 + beqlr /* for 601, do nothing */ + /* 603/604 processor - use invalidate-all bit in HID0 */ + mfspr r3,HID0 + ori r3,r3,HID0_ICFI + mtspr HID0,r3 + isync + blr + +/* + * Invalidate L1 data cache. + */ +_GLOBAL(invalidate_l1_data_cache) + mfspr r3,HID0 + ori r3,r3,HID0_DCFI + mtspr HID0,r3 + isync + blr + +/* + * Flush data cache. + */ +_GLOBAL(flush_data_cache) + lis r3,0 + lis r5,CACHE_LINE_SIZE +flush: + cmp 0,1,r3,r5 + bge done + lwz r5,0(r3) + lis r5,CACHE_LINE_SIZE + addi r3,r3,0x4 + b flush +done: + blr +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * This is a no-op on the 601. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 // align r3 down to cache line + subf r4,r3,r4 // r4 = offset of stop from start of cache line + add r4,r4,r5 // r4 += cache_line_size-1 + srwi. r4,r4,LG_CACHE_LINE_SIZE // r4 = number of cache lines to flush + beqlr // if r4 == 0 return + mtctr r4 // ctr = r4 + + sync +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbf 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbf's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * Flush a particular page from the data cache to RAM. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * This is a no-op on the 601 which has a unified cache. + * + * void __flush_page_to_ram(void *page) + */ +_GLOBAL(__flush_page_to_ram) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + rlwinm r3,r3,0,0,19 /* Get page base address */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 + mr r6,r3 +0: dcbst 0,r3 /* Write line to ram */ + addi r3,r3,CACHE_LINE_SIZE + bdnz 0b + sync + mtctr r4 +1: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Flush a particular page from the instruction cache. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * This is a no-op on the 601 which has a unified cache. + * + * void __flush_icache_page(void *page) + */ +_GLOBAL(__flush_icache_page) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 +1: icbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Clear a page using the dcbz instruction, which doesn't cause any + * memory traffic (except to write out any cache lines which get + * displaced). This only works on cacheable memory. + */ +_GLOBAL(clear_page) + li r0,4096/CACHE_LINE_SIZE + mtctr r0 +1: dcbz 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + blr + +/* + * Enable L1 Instruction cache + */ +_GLOBAL(icache_enable) + mfspr r3, HID0 + li r5, HID0_ICFI|HID0_ILOCK + andc r3, r3, r5 + ori r3, r3, HID0_ICE + ori r5, r3, HID0_ICFI + mtspr HID0, r5 + mtspr HID0, r3 + isync + blr + +/* + * Disable L1 Instruction cache + */ +_GLOBAL(icache_disable) + mfspr r3, HID0 + li r5, 0 + ori r5, r5, HID0_ICE + andc r3, r3, r5 + mtspr HID0, r3 + isync + blr + +/* + * Is instruction cache enabled? + */ +_GLOBAL(icache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_ICE + blr + + +_GLOBAL(l1dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + +/* + * Enable data cache(s) - L1 and optionally L2 + * Calls l2cache_enable. LR saved in r5 + */ +_GLOBAL(dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync +#ifdef CFG_L2 + mflr r5 + bl l2cache_enable /* uses r3 and r4 */ + sync + mtlr r5 +#endif + blr + + +/* + * Disable data cache(s) - L1 and optionally L2 + * Calls flush_data_cache and l2cache_disable_no_flush. + * LR saved in r4 + */ +_GLOBAL(dcache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + li r5, HID0_DCE|HID0_DCFI + andc r3, r3, r5 /* no enable, no invalidate */ + mtspr HID0, r3 + sync +#ifdef CFG_L2 + bl l2cache_disable_no_flush /* uses r3 */ +#endif + mtlr r4 /* restore link register */ + blr + +/* + * Is data cache enabled? + */ +_GLOBAL(dcache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_DCE + blr + +/* + * Invalidate L2 cache using L2I and polling L2IP + */ +_GLOBAL(l2cache_invalidate) + sync + oris r3, r3, L2CR_L2I@h + sync + mtspr l2cr, r3 + sync +invl2: + mfspr r3, l2cr + andi. r3, r3, L2CR_L2IP + bne invl2 + /* turn off the global invalidate bit */ + mfspr r3, l2cr + rlwinm r3, r3, 0, 11, 9 + sync + mtspr l2cr, r3 + sync + blr + +/* + * Enable L2 cache + * Calls l2cache_invalidate. LR is saved in r4 + */ +_GLOBAL(l2cache_enable) + mflr r4 /* save link register */ + bl l2cache_invalidate /* uses r3 */ + sync + lis r3, L2_ENABLE@h + ori r3, r3, L2_ENABLE@l + mtspr l2cr, r3 + isync + mtlr r4 /* restore link register */ + blr + +/* + * Disable L2 cache + * Calls flush_data_cache. LR is saved in r4 + */ +_GLOBAL(l2cache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mtlr r4 /* restore link register */ +l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ + lis r3, L2_INIT@h + ori r3, r3, L2_INIT@l + mtspr l2cr, r3 + isync + blr diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index 7df519e..07331b3 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -59,8 +59,12 @@ get_cpu_type(void) case 0x0008: type = CPU_750; - if (((pvr >> 8) & 0xff) == 0x22) { - type = CPU_750CX; + if (((pvr >> 8) & 0xff) == 0x01) { + type = CPU_750CX; /* old CX (80100 and 8010x?)*/ + } else if (((pvr >> 8) & 0xff) == 0x22) { + type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ + } else if (((pvr >> 8) & 0xff) == 0x33) { + type = CPU_750CX; /* CXe (83311) */ } else if (((pvr >> 12) & 0xF) == 0x3) { type = CPU_755; } @@ -93,7 +97,7 @@ checkcpu(long clock) switch (type) { case CPU_750CX: - printf ("750CX(e) v2.%d", pvr & 0xf); + printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", (pvr>>8) & 0xf, pvr & 0xf); goto PR_CLK; case CPU_750: @@ -150,29 +154,44 @@ checkdcache(void) /* ------------------------------------------------------------------------- */ -/* note: this does NOT work. Using the RTC to reset the system - * didn't seem to work either. so, currently there is no way to - * software reset the galileo eval board. [josh] */ +static inline void +soft_restart(unsigned long addr) +{ + /* SRR0 has system reset vector, SRR1 has default MSR value */ + /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + __asm__ __volatile__ + ("\n\ + mtspr 26,%0 + li 4,(1<<6) + mtspr 27,4 + rfi + " : : "r" (addr)); + while(1); /* not reached */ +} + #ifndef CONFIG_PCIPPC2 +/* no generic way to do board reset. simply call soft_reset. */ void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - ulong msr, addr; - - /* XXX */ - puts("do_reset unimplemented\n"); - return; + ulong addr; + /* flush and disable I/D cache */ + __asm__ __volatile__ + ("\n\ + mfspr 3,1008 + ori 5,5,0xcc00 + ori 4,3,0xc00 + andc 5,3,5 + sync + mtspr 1008,4 + isync + sync + mtspr 1008,5 + isync + sync + "); - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0" : "=r"(msr) : ); - msr &= ~(MSR_ME|MSR_EE|MSR_IR|MSR_DR); - __asm__ __volatile__ ("mtmsr %0" : : "r"(msr) ); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ #ifdef CFG_RESET_ADDRESS addr = CFG_RESET_ADDRESS; #else @@ -184,7 +203,8 @@ do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ addr = CFG_MONITOR_BASE - sizeof (ulong); #endif - ((void (*)(void ))addr)(); + soft_restart(addr); + while(1); /* not reached */ } #endif diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index 94e5215..0ad95ea 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000, 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,25 @@ #include <74xx_7xx.h> #include +static const int hid1_multipliers_x_10[] = { + 25, /* 0000 - 2.5x */ + 75, /* 0001 - 7.5x */ + 70, /* 0010 - 7x */ + 10, /* 0011 - bypass */ + 20, /* 0100 - 2x */ + 65, /* 0101 - 6.5x */ + 100, /* 0110 - 10x */ + 45, /* 0111 - 4.5x */ + 30, /* 1000 - 3x */ + 55, /* 1001 - 5.5x */ + 40, /* 1010 - 4x */ + 50, /* 1011 - 5x */ + 80, /* 1100 - 8x */ + 60, /* 1101 - 6x */ + 35, /* 1110 - 3.5x */ + 0 /* 1111 - off */ +}; + /* ------------------------------------------------------------------------- */ /* @@ -36,19 +55,15 @@ * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] */ -ulong -get_gclk_freq (void) +ulong get_gclk_freq (void) { - /* figure out a way to measure the clock speed? XXX */ - return CFG_CPU_CLK; + return CFG_BUS_CLK * hid1_multipliers_x_10[get_hid1 () >> 28] / 10; } /* ------------------------------------------------------------------------- */ -ulong -get_bus_freq (ulong gclk_freq) +ulong get_bus_freq (ulong gclk_freq) { - /* woohoo XXX */ return CFG_BUS_CLK; } diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 855dd7f..694fe9c 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -80,15 +80,16 @@ .long 0x27051956 /* PPCBOOT Magic Number */ .globl version_string version_string: - .ascii PPCBOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii PPCBOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start _start: li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ b boot_cold + sync . = EXC_OFF_SYS_RESET + 0x10 @@ -96,9 +97,10 @@ _start: _start_warm: li r21, BOOTFLAG_WARM /* Software reboot */ b boot_warm + sync /* the boot code is located below the exception table */ - + .globl _start_of_vectors _start_of_vectors: @@ -170,7 +172,7 @@ SystemCall: cmplw 0, r0, r12 bge 1f - + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ add r11,r11,r0 lwz r11,0(r11) @@ -216,8 +218,9 @@ _back: STD_EXCEPTION(0xe00, Trap_0e, UnknownException) STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. + /* + * On the MPC8xx, this is a software emulation interrupt. It + * occurs for all unimplemented and illegal instructions. */ STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) @@ -251,39 +254,33 @@ boot_warm: mtspr HID0, r0 sync mtmsr 0 - bl invalidate_bats + sync #ifdef CFG_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l + sync mtspr l2cr, r3 #endif #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) .long 0x7e00066c - /* dssall instruction, gas doesn't have it yet */ - /* ...for altivec, data stream stop all */ - /* this probably isn't needed unless we warm */ - /* (software) reboot ppcboot */ + /* + * dssall instruction, gas doesn't have it yet + * ...for altivec, data stream stop all this probably + * isn't needed unless we warm (software) reboot ppcboot + */ #endif #ifdef CFG_L2 /* invalidate the L2 cache */ + bl l2cache_invalidate sync - oris r3, r3, L2CR_L2I@h - mtspr l2cr, r3 - sync - -invl2: - mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP - bne invl2 - - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - mtspr l2cr, r3 +#endif +#ifdef CFG_BOARD_ASM_INIT + /* do early init */ + bl board_asm_init #endif /* @@ -307,12 +304,29 @@ in_flash: /* setup the bats */ bl setup_bats + sync - /* enable and invalidate the data cache */ - bl dcache_enable + /* + * Cache must be enabled here for stack-in-cache trick. + * This means we need to enable the BATS. + * This means: + * 1) for the EVB, original gt regs need to be mapped + * 2) need to have an IBAT for the 0xf region, + * we are running there! + * Cache should be turned on after BATs, since by default + * everything is write-through. + * The init-mem BAT can be reused after reloc. The old + * gt-regs BAT can be reused after board_init_f calls + * board_pre_init (EVB only). + */ /* enable address translation */ bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ + bl l1dcache_enable + sync #ifdef CFG_INIT_RAM_LOCK /* Allocate Initial RAM in data cache. @@ -327,8 +341,7 @@ in_flash: addi r3, r3, 32 bdnz 1b - /* Lock the data cache - */ + /* Lock the data cache */ mfspr r0, HID0 ori r0, r0, 0x1000 sync @@ -349,12 +362,14 @@ in_flash: /* run low-level CPU init code (from Flash) */ bl cpu_init_f + sync mr r3, r21 /* r3: BOOTFLAG */ /* run 1st part of board init code (from Flash) */ bl board_init_f + sync /* NOTREACHED */ @@ -547,82 +562,6 @@ int_return: SYNC rfi -/* Cache functions. XXX fix these, I think they're broken [josh]. -*/ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, (HID0_ICE | HID0_ICFI) - sync - mtspr HID0, r3 - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - li r4, 0 - ori r4, r4, HID0_ICE - andc r3, r3, r4 - sync - mtspr HID0, r3 - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - andi. r3, r3, HID0_ICE - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - mr r2, r3 - ori r3, r3, (HID0_DCI | HID0_DCE) - ori r2, r2, HID0_DCE - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - li r4, HID0_DCE - andc r3, r3, r4 - mr r2, r3 - ori r3, r3, HID0_DCI - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync - blr - - .globl dcache_lock -dcache_lock: - mfspr r3, HID0 - ori r3, r3, HID0_DLOCK - sync - mtspr HID0, r3 - isync - sync - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - andi. r3, r3, HID0_DCE - blr - - .globl l2_enable -l2_enable: - addis r3, r0, L2_ENABLE@h - ori r3, r3, L2_ENABLE@l - mtspr l2cr, r3 - blr - .globl dc_read dc_read: blr @@ -676,7 +615,14 @@ relocate_code: */ #ifdef CONFIG_ECC bl board_relocate_rom -#else + sync + mr r3, r10 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */ + ori r5, r5, CFG_MONITOR_LEN@l + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ +#else cmplw cr1,r3,r4 addi r0,r5,3 srwi. r0,r0,2 @@ -750,11 +696,11 @@ in_ram: add r0,r0,r11 stw r0,0(r3) bdnz 1b - + /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. - */ + */ 2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 @@ -768,7 +714,7 @@ in_ram: stw r0,0(r4) bdnz 3b 4: -clear_bss: +/* clear_bss: */ /* * Now clear BSS segment */ @@ -785,11 +731,13 @@ clear_bss: cmplw 0, r3, r4 bne 5b 6: - mr r3, r9 /* Board Info pointer */ mr r4, r10 /* Destination Address */ bl after_reloc + /* not reached - end relocate_code */ +/*-----------------------------------------------------------------------*/ + /* Problems accessing "end" in C, so do it here */ .globl get_endaddr get_endaddr: @@ -845,7 +793,7 @@ trap_init: addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 3b - + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 4: diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 6734f3e..c9eb8d4 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -392,7 +392,7 @@ static char *mkmodestr(unsigned long mode, char *str) char c; switch (mode & __S_IFMT) { - case __S_IFDIR: str[0]=(mode & __S_ISVTX)?'t':'d'; break; + case __S_IFDIR: str[0]='d'; break; case __S_IFBLK: str[0]='b'; break; case __S_IFCHR: str[0]='c'; break; case __S_IFIFO: str[0]='f'; break; @@ -408,8 +408,9 @@ static char *mkmodestr(unsigned long mode, char *str) mask=mask<<1; } - if((mode & __S_ISUID) && (mode & __S_IXUSR)) str[3]='s'; - if((mode & __S_ISGID) && (mode & __S_IXGRP)) str[6]='s'; + if(mode & __S_ISUID) str[3]=(mode & __S_IXUSR)?'s':'S'; + if(mode & __S_ISGID) str[6]=(mode & __S_IXGRP)?'s':'S'; + if(mode & __S_ISVTX) str[9]=(mode & __S_IXOTH)?'t':'T'; str[10]='\0'; return str; } @@ -705,6 +706,7 @@ jffs2_1pass_build_lists(struct part_info * part, struct b_lists * pL) u32 counter = 0; u32 counter4 = 0; u32 counterF = 0; + u32 counterN = 0; // turn off the lcd. Refreshing the lcd adds 50% overhead to the // jffs2 list building enterprise nope. in newer versions the overhead is @@ -739,7 +741,8 @@ jffs2_1pass_build_lists(struct part_info * part, struct b_lists * pL) } else if (node->nodetype == JFFS2_NODETYPE_DIRENT && dirent_crc((struct jffs2_raw_dirent *) node) && dirent_name_crc((struct jffs2_raw_dirent *) node)) { - printf("\b\b. "); + if (! (counterN%100)) + printf("\b\b. "); #if 0 printf("Found DIRENT @ 0x%lx\n", offset); putstr("\r\nbuild_lists:p&l ->"); @@ -763,6 +766,7 @@ jffs2_1pass_build_lists(struct part_info * part, struct b_lists * pL) #endif if (!pL->dirListHead) pL->dirListHead = pL->dirListTail; + counterN++; } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { if (node->totlen != sizeof(struct jffs2_unknown_node)) printf("OOPS Cleanmarker has bad size %d != %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h index a9ce96d..ca0af1f 100644 --- a/fs/jffs2/jffs2_private.h +++ b/fs/jffs2/jffs2_private.h @@ -33,8 +33,8 @@ struct b_jffs2_info { static inline int hdr_crc(struct jffs2_unknown_node *node) { - u32 crc = crc32_no_comp(0, node, sizeof(struct jffs2_unknown_node) - 4); - u32 crc_blah = crc32_no_comp(~0, node, sizeof(struct jffs2_unknown_node) - 4); + u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); + u32 crc_blah = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); crc_blah ^= ~0; @@ -48,7 +48,7 @@ hdr_crc(struct jffs2_unknown_node *node) static inline int dirent_crc(struct jffs2_raw_dirent *node) { - if (node->node_crc != crc32_no_comp(0, node, sizeof(struct jffs2_raw_dirent) - 8)) { + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) { return 0; } else { return 1; @@ -58,7 +58,7 @@ dirent_crc(struct jffs2_raw_dirent *node) static inline int dirent_name_crc(struct jffs2_raw_dirent *node) { - if (node->name_crc != crc32_no_comp(0, &(node->name), node->nsize)) { + if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) { return 0; } else { return 1; @@ -68,7 +68,7 @@ dirent_name_crc(struct jffs2_raw_dirent *node) static inline int inode_crc(struct jffs2_raw_inode *node) { - if (node->node_crc != crc32_no_comp(0, node, sizeof(struct jffs2_raw_inode) - 8)) { + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) { return 0; } else { return 1; diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 7d555b5..193ba6c 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -116,6 +116,11 @@ typedef enum __cpu_t { extern cpu_t get_cpu_type(void); +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + static __inline__ unsigned long get_msr (void) { unsigned long msr; @@ -153,5 +158,4 @@ static __inline__ void set_hid1 (unsigned long hid1) } #endif /* __ASSEMBLY__ */ - #endif /* __MPC74XX_H__ */ diff --git a/include/asm/cache.h b/include/asm/cache.h index c45fd84..35b074d 100644 --- a/include/asm/cache.h +++ b/include/asm/cache.h @@ -33,7 +33,8 @@ #if defined(__KERNEL__) && !defined(__ASSEMBLY__) extern void flush_dcache_range(unsigned long start, unsigned long stop); - +extern void clean_dcache_range(unsigned long start, unsigned long stop); +extern void invalidate_dcache_range(unsigned long start, unsigned long stop); #endif /* __ASSEMBLY__ */ /* prep registers for L2 */ diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h index 2856907..ccf9919 100644 --- a/include/cmd_bsp.h +++ b/include/cmd_bsp.h @@ -175,17 +175,17 @@ int do_crayL1 (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]); #define ZUMA_TBL_ENTRY MK_CMD_TBL_ENTRY( \ "zinit", 5, 1, 0, do_zuma_init_pbb, \ - "zinit - init zuma pbb\n", \ + "zinit - init zuma pbb\n", \ "\n" \ " - init zuma pbb\n" \ ), MK_CMD_TBL_ENTRY( \ "zdtest", 6, 3, 1, do_zuma_test_dma, \ - "zdtest - run dma test\n", \ + "zdtest - run dma test\n", \ "[cmd [count]]\n" \ " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" \ ), MK_CMD_TBL_ENTRY( \ "zminit", 5, 1, 0, do_zuma_init_mbox, \ - "zminit - init zuma mbox\n", \ + "zminit - init zuma mbox\n", \ "\n" \ " - init zuma mbox\n" \ ), diff --git a/include/cmd_jffs2.h b/include/cmd_jffs2.h index 5ebc23d..062ae78 100644 --- a/include/cmd_jffs2.h +++ b/include/cmd_jffs2.h @@ -30,20 +30,20 @@ #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #define CMD_TBL_JFFS2 MK_CMD_TBL_ENTRY( \ "fsload", 5, 3, 0, do_jffs2_fsload, \ - "fsload - load binary file from a filesystem image\n", \ + "fsload - load binary file from a filesystem image\n", \ "[ off ] [ filename ]\n" \ " - load binary file from flash bank\n" \ " with offset 'off'\n" \ ), \ MK_CMD_TBL_ENTRY( \ "fsinfo", 5, 1, 1, do_jffs2_fsinfo, \ - "fsinfo - print information about filesystems\n", \ + "fsinfo - print information about filesystems\n", \ "\n" \ " - print information about filesystems\n" \ ), \ MK_CMD_TBL_ENTRY( \ "ls", 2, 2, 1, do_jffs2_ls, \ - "ls - list files in a directory (default /)\n", \ + "ls - list files in a directory (default /)\n", \ "[ directory ]\n" \ " - list files in a directory.\n" \ ), diff --git a/include/config_EVB64260.h b/include/config_EVB64260.h index 2491f9f..e2e8f5c 100644 --- a/include/config_EVB64260.h +++ b/include/config_EVB64260.h @@ -34,7 +34,7 @@ #include #endif -/* XXX #include "local.h" XXX */ +#include "../board/evb64260/local.h" /* * High Level Configuration Options @@ -154,6 +154,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfff00000 +#define CFG_RESET_ADDRESS 0xfff00100 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc */ diff --git a/include/config_ZUMA.h b/include/config_ZUMA.h index feb3bae..ca5a850 100644 --- a/include/config_ZUMA.h +++ b/include/config_ZUMA.h @@ -34,7 +34,7 @@ #include #endif -/* XXX #include "local.h" XXX */ +#include "../board/evb64260/local.h" #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ #define ZUMA_NTL 1 /* temporary, will rename to something nicer */ @@ -48,6 +48,7 @@ /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT +#define CFG_BOARD_ASM_INIT #define CFG_BOARD_NAME "Zuma APv2" @@ -99,10 +100,12 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_MII #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_BSP | \ CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ CFG_CMD_DATE) /* Flash banks JFFS2 should use */ @@ -129,7 +132,7 @@ #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x300000 /* default load address */ +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ #define CFG_HZ 1000 /* decr freq: 1ms ticks */ @@ -162,9 +165,10 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfff00000 +#define CFG_RESET_ADDRESS 0xfff00100 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ /* areas to map different things with the GT in physical space */ #define CFG_DRAM_BANKS 4 @@ -355,6 +359,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_BOARD_ASM_INIT 1 - #endif /* __CONFIG_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h index abec978..59dd220 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -16,8 +16,8 @@ extern "C" { #define __S_IFSOCK 0140000 /* named socket */ #define __S_IFIFO 0010000 /* fifo */ -#define __S_ISLNK(m) (((m)&_IFMT) == _IFLNK) -#define __S_ISSOCK(m) (((m)&_IFMT) == _IFSOCK) +#define __S_ISLNK(m) (((m)&__S_IFMT) == __S_IFLNK) +#define __S_ISSOCK(m) (((m)&__S_IFMT) == __S_IFSOCK) #define __S_ISUID 0004000 /* set user id on execution */ #define __S_ISGID 0002000 /* set group id on execution */ diff --git a/include/ppcboot.h b/include/ppcboot.h index e750347..683cf5c 100644 --- a/include/ppcboot.h +++ b/include/ppcboot.h @@ -195,6 +195,7 @@ void inline setenv (char *, char *); defined(CONFIG_CPCI405) || \ defined(CONFIG_CPCIISER4) || \ defined(CONFIG_DASA_SIM) || \ + defined(CONFIG_EVB64260) || \ defined(CONFIG_DU405) || \ defined(CONFIG_ERIC) || \ defined(CONFIG_EVB64260) || \