From: Siddharth Vadapalli Date: Thu, 9 Mar 2023 06:35:14 +0000 (+0530) Subject: phy: ti: gmii-sel: Enable SGMII mode for J721E X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=2de2e49b3226cc6252c7dbf1a543e7546db416d3;p=linux.git phy: ti: gmii-sel: Enable SGMII mode for J721E TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul --- diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index f3da6b020247..c87118cb2af9 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -230,7 +230,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, };