From: Anup Patel <anup@brainfault.org>
Date: Tue, 4 Dec 2018 13:55:06 +0000 (+0530)
Subject: RISC-V: defconfig: Enable RISC-V SBI earlycon support
X-Git-Tag: v5.0-rc1~161^2~2^2~1
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=2b3f786408c5400705ed722ab2f3065e86272857;p=users%2Fwilly%2Fxarray.git

RISC-V: defconfig: Enable RISC-V SBI earlycon support

This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index ef4f15df9adf..f399659d3b8d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -46,6 +46,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
 CONFIG_HVC_RISCV_SBI=y
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_DRM=y