From: Tom Lendacky <thomas.lendacky@amd.com>
Date: Fri, 15 Dec 2017 17:16:54 +0000 (-0800)
Subject: x86/cpu/AMD: Add speculative control support for AMD
X-Git-Tag: v4.1.12-124.31.3~1399
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=28b8f4f0c111a6e2489a1422134d37e297e33720;p=users%2Fjedix%2Flinux-maple.git

x86/cpu/AMD: Add speculative control support for AMD

Add speculative control support for AMD processors. For AMD, speculative
control is indicated as follows:

  CPUID EAX=0x00000007, ECX=0x00 return EDX[26] indicates support for
  both IBRS and IBPB.

  CPUID EAX=0x80000008, ECX=0x00 return EBX[12] indicates support for
  just IBPB.


Orabug: 27344012
CVE: CVE-2017-5715

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Tim Chen <tim.c.chen@linux.inte.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

[Backport: We don't have 39c06df4dc10a "x86/cpufeature: Cleanup get_cpu_cap()"
 which adds a nice enum and we neither do we have 2167ceabf3416
 "x86/cpu: Add CLZERO detection". As such we just a partial backport
 of the last one and only look for one specific bit (12).]

Reviewed-by: John Haxby <john.haxby@oracle.com>
Signed-off-by: Kirtikar Kashyap <kirtikar.kashyap@oracle.com>
---

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index cd6b45162058..5ffc01e9d027 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
 #include <asm/disabled-features.h>
 #endif
 
-#define NCAPINTS	13	/* N 32-bit words worth of info */
+#define NCAPINTS	14	/* N 32-bit words worth of info */
 #define NBUGINTS	1	/* N 32-bit bug flags */
 
 /*
@@ -256,6 +256,9 @@
 /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
 #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
 
+/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
+#define X86_FEATURE_IBPB                (13*32+12) /* Indirect Branch Prediction Barrier */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5732326ec126..f71484053a91 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -681,10 +681,15 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 	}
 
 	if (c->extended_cpuid_level >= 0x80000008) {
-		u32 eax = cpuid_eax(0x80000008);
+		u32 eax, ebx, ecx, edx;
+
+		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
 
 		c->x86_virt_bits = (eax >> 8) & 0xff;
 		c->x86_phys_bits = eax & 0xff;
+		/* Only look for X86_FEATURE_IBPB. */
+		ebx &= (1u<<12);
+		c->x86_capability[X86_FEATURE_IBPB / 32] = ebx;
 	}
 #ifdef CONFIG_X86_32
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 77f1e0327d75..61216c821682 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -94,6 +94,11 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
 				sysctl_ibrs_enabled = 1;
 			if (ibpb_inuse)
 				sysctl_ibpb_enabled = 1;
+		} else if (boot_cpu_has(X86_FEATURE_IBPB)) {
+			printk_once(KERN_INFO "FEATURE IBPB Present\n");
+			set_ibpb_supported();
+			if (ibpb_inuse)
+				sysctl_ibpb_enabled = 1;
 		} else {
 			printk(KERN_INFO "FEATURE SPEC_CTRL Not Present\n");
 		}