From: Dillon Varone <dillon.varone@amd.com>
Date: Fri, 2 Aug 2024 17:50:10 +0000 (-0400)
Subject: drm/amd/display: Set max VTotal cap for dcn401
X-Git-Tag: configfs-6.13-2024-11-19~386^2~17^2~135
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=24f483ba49c9acc1139a0b4cbfd1b122fbe1ed7f;p=users%2Fhch%2Fconfigfs.git

drm/amd/display: Set max VTotal cap for dcn401

[WHY&HOW]
Set max VTotal cap for dcn401 because VTotal
register is only 16 bits wide on dcn401.

Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index ec676d269d33..02e63b95c36d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1822,6 +1822,7 @@ static bool dcn401_resource_construct(
 	dc->caps.edp_dsc_support = true;
 	dc->caps.extended_aux_timeout_support = true;
 	dc->caps.dmcub_support = true;
+	dc->caps.max_v_total = (1 << 15) - 1;
 
 	if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
 		dc->caps.dcc_plane_width_limit = 7680;