From: Boris Ostrovsky Date: Tue, 26 Mar 2019 22:45:55 +0000 (-0400) Subject: Revert "x86/bugs: Add AMD's SPEC_CTRL MSR usage" X-Git-Tag: v4.1.12-124.31.3~229 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=22f06f2a15446f76eaee0fb504b6be220d57c092;p=users%2Fjedix%2Flinux-maple.git Revert "x86/bugs: Add AMD's SPEC_CTRL MSR usage" This reverts commit 6ed384dcb12d6b7f2b8a448810e56206b9db4fb7. Revert due to performance regression. Orabug: 29542029 Signed-off-by: Boris Ostrovsky Reviewed-by: Mihai Carabas Signed-off-by: Brian Maly --- diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index c39093d904a0..edf15b54395c 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -73,7 +73,6 @@ */ #define X86_FEATURE_L1TF_PTEINV ( 2*32+0) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_FLUSH_L1D ( 2*32+1) /* Flush L1D cache */ -#define X86_FEATURE_AMD_SSBD ( 2*32+2) /* "" Speculative Store Bypass Disable */ /* Other features, Linux-defined mapping, word 3 */ /* This range is used for feature bits which conflict or are synthesized */ diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c index e2b05123c7fc..61c342a1afaa 100644 --- a/arch/x86/kernel/cpu/bugs_64.c +++ b/arch/x86/kernel/cpu/bugs_64.c @@ -1033,18 +1033,11 @@ static void __init ssb_init(void) if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) { /* - * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may - * use a completely different MSR and bit dependent on family. + * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses + * a completely different MSR and bit dependent on family. */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: - case X86_VENDOR_AMD: - if (ssb_mode == SPEC_STORE_BYPASS_DISABLE && - !static_cpu_has(X86_FEATURE_IBRS)) { - x86_amd_ssbd_enable(); - break; - } - x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; x86_spec_ctrl_priv |= SPEC_CTRL_SSBD; @@ -1053,6 +1046,10 @@ static void __init ssb_init(void) update_cpu_spec_ctrl_all(); break; + case X86_VENDOR_AMD: + if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) + x86_amd_ssbd_enable(); + break; } } if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9fa8a129425c..ad96345b64a7 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -760,8 +760,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c, enum get_cpu_cap_behavior behavior) set_cpu_cap(c, X86_FEATURE_IBRS); if (ebx & BIT(15)) set_cpu_cap(c, X86_FEATURE_STIBP); - if (ebx & BIT(24)) - set_cpu_cap(c, X86_FEATURE_AMD_SSBD); if (ebx & BIT(25)) set_cpu_cap(c, X86_FEATURE_VIRT_SSBD); } diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 1e5793aab0f2..894acfa0a7f0 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -56,6 +56,7 @@ u64 kvm_supported_xcr0(void) return xcr0; } + int kvm_update_cpuid(struct kvm_vcpu *vcpu) { struct kvm_cpuid_entry2 *best; @@ -357,7 +358,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_80000008_ebx_x86_features = - KF(IBPB) | KF(IBRS) | KF(AMD_SSBD) | KF(VIRT_SSBD); + KF(IBPB) | KF(IBRS) | KF(VIRT_SSBD); /* all calls to cpuid_count() should be made on the same cpu */ get_cpu(); @@ -596,12 +597,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, if ( !boot_cpu_has(X86_FEATURE_IBPB) ) entry->ebx &= ~(1u << KVM_CPUID_BIT_IBPB); - /* - * The preference is to use SPEC CTRL MSR instead of the - * VIRT_SPEC MSR. - */ - if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && - !boot_cpu_has(X86_FEATURE_AMD_SSBD)) + if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) entry->ebx |= KF(VIRT_SSBD); break; } diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index 61ccddc01f20..24a166ad0a98 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -131,7 +131,6 @@ static inline bool guest_cpuid_has_mpx(struct kvm_vcpu *vcpu) /* These are scattered features in cpufeatures.h. */ #define KVM_CPUID_BIT_IBPB 12 -#define KVM_CPUID_BIT_AMD_SSBD 24 #define KVM_CPUID_BIT_VIRT_SSBD 25 #define KVM_CPUID_BIT_IBRS 26 #define KVM_CPUID_BIT_STIBP 27 @@ -161,12 +160,4 @@ static inline bool guest_cpuid_has_ssbd(struct kvm_vcpu *vcpu) best = kvm_find_cpuid_entry(vcpu, 7, 0); return best && (best->edx & KF(SSBD)); } - -static inline bool guest_cpuid_has_amd_ssbd(struct kvm_vcpu *vcpu) -{ - struct kvm_cpuid_entry2 *best; - - best = kvm_find_cpuid_entry(vcpu, 7, 0); - return best && (best->edx & KF(AMD_SSBD)); -} #endif diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index ec7251565d6c..5b54efa669c8 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -3191,7 +3191,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && !guest_cpuid_has_ibrs(vcpu) && - !guest_cpuid_has_amd_ssbd(vcpu)) + !guest_cpuid_has_ssbd(vcpu)) return 1; msr_info->data = svm->spec_ctrl; @@ -3324,11 +3324,11 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) case MSR_IA32_SPEC_CTRL: if (!msr->host_initiated && !guest_cpuid_has_ibrs(vcpu) && - !guest_cpuid_has_amd_ssbd(vcpu)) + !guest_cpuid_has_ssbd(vcpu)) return 1; /* The STIBP bit doesn't fault even if it's not advertised */ - if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) + if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP)) return 1; svm->spec_ctrl = data;