From: Wenjing Liu Date: Wed, 23 Aug 2017 21:02:34 +0000 (-0400) Subject: drm/amd/display: do not reset lane count in EQ fallback X-Git-Tag: v4.15-rc1~56^2~23^2~128 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=1cf49dea28dfc76f0816a4bc73c2ab975c72f55d;p=users%2Fwilly%2Flinux.git drm/amd/display: do not reset lane count in EQ fallback [Description] According to DP1.4 specs we should not reset lane count back when falling back in failing EQ training. This causes PHY test pattern compliance to fail as infinite LT when LT fails EQ to 4 RBR and fails CR in a loop. Signed-off-by: Wenjing Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e19447d526ea..446e2933474c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting( current_link_setting->lane_count); } else if (!reached_minimum_link_rate (current_link_setting->link_rate)) { - current_link_setting->lane_count = - initial_link_settings.lane_count; current_link_setting->link_rate = reduce_link_rate( current_link_setting->link_rate);