From: wdenk Date: Fri, 20 Sep 2002 09:34:14 +0000 (+0000) Subject: Misc patches / cleanup. X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=1bf289ffeb2ad305ec13413fd6689f819a38025d;p=users%2Frw%2Fppcboot.git Misc patches / cleanup. --- diff --git a/README b/README index ad7a837..18c2c60 100644 --- a/README +++ b/README @@ -116,6 +116,7 @@ Directory Hierarchy: - board/cray/ Files specific to boards manufactured by Cray - board/cray/L1 Files specific to L1 boards - board/cu824 Files specific to CU824 boards +- board/ebony Files specific to IBM Ebony board - board/eric Files specific to ERIC boards - board/esd/ Files specific to boards manufactured by ESD - board/esd/adciop Files specific to ADCIOP boards @@ -243,25 +244,27 @@ The following options need to be configured: or CONFIG_MPC824X, CONFIG_MPC8260 or CONFIG_IOP480 or CONFIG_405GP + or CONFIG_440 or CONFIG_MPC74xx - Board Type: Define exactly one of - CONFIG_ADCIOP, CONFIG_IP860, CONFIG_RPXsuper, - CONFIG_ADS860, CONFIG_IPHASE4539, CONFIG_SM850, - CONFIG_AMX860, CONFIG_IVML24, CONFIG_SPD823TS, - CONFIG_AR405, CONFIG_IVML24_128, CONFIG_SXNI855T, - CONFIG_BAB750, CONFIG_IVML24_256, CONFIG_Sandpoint8240, - CONFIG_CANBT, CONFIG_IVMS8, CONFIG_Sandpoint8245, - CONFIG_CCM, CONFIG_IVMS8_128, CONFIG_TQM823L, - CONFIG_CPCI405, CONFIG_IVMS8_256, CONFIG_TQM850L, - CONFIG_CPCI4052, CONFIG_LANTEC, CONFIG_TQM855L, - CONFIG_CPCIISER4, CONFIG_MBX, CONFIG_TQM860L, - CONFIG_CPU86, CONFIG_MBX860T, CONFIG_TQM8260, - CONFIG_CRAYL1, CONFIG_MHPC, CONFIG_TTTech, - CONFIG_CU824, CONFIG_MIP405, CONFIG_W7OLMC, - CONFIG_DASA_SIM, CONFIG_MOUSSE, CONFIG_W7OLMG, - CONFIG_DU405, CONFIG_MPC8260ADS, CONFIG_WALNUT405, + CONFIG_ADCIOP, CONFIG_ICU862 CONFIG_RPXsuper, + CONFIG_ADS860, CONFIG_IP860, CONFIG_SM850, + CONFIG_AMX860, CONFIG_IPHASE4539, CONFIG_SPD823TS, + CONFIG_AR405, CONFIG_IVML24, CONFIG_SXNI855T, + CONFIG_BAB7xx, CONFIG_IVML24_128, CONFIG_Sandpoint8240, + CONFIG_CANBT, CONFIG_IVML24_256, CONFIG_Sandpoint8245, + CONFIG_CCM, CONFIG_IVMS8, CONFIG_TQM823L, + CONFIG_CPCI405, CONFIG_IVMS8_128, CONFIG_TQM850L, + CONFIG_CPCI4052, CONFIG_IVMS8_256, CONFIG_TQM855L, + CONFIG_CPCIISER4, CONFIG_LANTEC, CONFIG_TQM860L, + CONFIG_CPU86, CONFIG_MBX, CONFIG_TQM8260, + CONFIG_CRAYL1, CONFIG_MBX860T, CONFIG_TTTech, + CONFIG_CU824, CONFIG_MHPC, CONFIG_UTX8245, + CONFIG_DASA_SIM, CONFIG_MIP405, CONFIG_W7OLMC, + CONFIG_DU405, CONFIG_MOUSSE, CONFIG_W7OLMG, + CONFIG_ELPPC, CONFIG_MPC8260ADS, CONFIG_WALNUT405, CONFIG_ERIC, CONFIG_MUSENKI, CONFIG_ZUMA, CONFIG_ESTEEM192E, CONFIG_MVS1, CONFIG_c2mon, CONFIG_ETX094, CONFIG_NX823, CONFIG_cogent_mpc8260, @@ -275,7 +278,8 @@ The following options need to be configured: CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260, CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, - CONFIG_ICU862 CONFIG_UTX8245 + CONFIG_EBONY + - CPU Module Type: (if CONFIG_COGENT is defined) Define exactly one of @@ -577,6 +581,17 @@ The following options need to be configured: devices. CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) +- NETWORK Support (PCI): + CONFIG_EEPRO100 + Support for Intel 82557/82559/82559ER chips. + Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom + write routine for first time initialisation. + + CONFIG_TULIP + Support for Digital 2114x chips. + Optional CONFIG_TULIP_SELECT_MEDIA for board specific + modem chip initialisation (KS8761/QS6611). + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405); define @@ -1568,7 +1583,7 @@ configurations; the following names are supported: FADS860T_config SXNI855T_config rsdproto_config FPS850L_config Sandpoint8240_config sbc8260_config GENIETV_config TQM823L_config PIP405_config - GEN860T_config + GEN860T_config EBONY_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/board/ebony/ebony.c b/board/ebony/ebony.c index 896cd87..6c37009 100644 --- a/board/ebony/ebony.c +++ b/board/ebony/ebony.c @@ -21,6 +21,8 @@ */ +extern long int spd_sdram (void); + #include #include "ebony.h" #include diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 5066fcb..91e0464 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -101,6 +101,10 @@ static uchar i2c_mm_last_chip; static uint i2c_mm_last_addr; static uint i2c_mm_last_alen; +#if defined(CFG_I2C_NOPROBES) +static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#endif + static int mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); extern int cmd_get_data_size(char* arg, int default_size); @@ -521,15 +525,36 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int j; +#if defined(CFG_I2C_NOPROBES) + int k, skip; +#endif printf("Valid chip addresses:"); for(j = 0; j < 128; j++) { +#if defined(CFG_I2C_NOPROBES) + skip = 0; + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ + skip = 1; + break; + } + } + if (skip) + continue; +#endif if(i2c_probe(j) == 0) { printf(" %02X", j); } } printf("\n"); +#if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); + puts ("\n"); +#endif + return 0; } diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 815b963..45ba7f3 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -1,6 +1,6 @@ PowerPC 440 - Last Update: August 27, 2002 + Last Update: September 11, 2002 ======================================================================= @@ -14,15 +14,15 @@ in the board/ebony directory. All testing was performed using the IBM Ebony board using both Rev B and Rev C silicon. However, since the Rev B. silicon has -extensive errata, support for Rev B. is minimal (it boots and +extensive errata, support for Rev B. is minimal (it boots, and features such as i2c, pci, tftpboot, etc. seem to work ok). The expectation is that all new board designs will be using -Rev C or later parts -- if not, you're in for a rough ride ;-) +Rev C or later parts -- if not, you may be in for a rough ride ;-) The ppc440 port does a fair job of keeping "board-specific" code out of the "cpu-specific" source. The goal of course was to provide mechanisms for each board to customize without having -to clutter the cpu-specific source with a lot of ifdefs. Many +to clutter the cpu-specific source with a lot of ifdefs. Most of these mechanisms are described in the following sections. @@ -84,6 +84,32 @@ handler table. This will probably be fixed soon ... or fix it yourself and submit a patch :-) +I2C +================= + +The i2c utilities have been tested on both Rev B. and Rev C. and +look good. The iprobe command implementation has been updated to +allow for 'skipped' addresses. Some i2c slaves are write only and +cause problems when a probe (read) is performed (for example the +CDCV850 clock controller at address 0x69 on the ebony board). + +To prevent probing certain addresses you can define the +CFG_I2C_NOPROBES macro in your board-specific header file. When +defined, all specified addresses are skipped during a probe. +The addresses that are skipped will be displayed in the output +of the iprobe command. + +For example, to prevent probing address 0x69, define the macro as +follows: + +#define CFG_I2C_NOPROBES {0x69} + +Similarly, to prevent probing addresses 0x69 and 0x70, define the +macro a: + +#define CFG_I2C_NOPROBES {0x69, 0x70} + + DDR SDRAM CONTROLLER ==================== @@ -123,12 +149,12 @@ pci_controller structure is initialized, the cpu-specific code will call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is defined. This routine is implemented by board-specific code & is where the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization task. If pci_pre_init() +settings and do other pre-initialization tasks. If pci_pre_init() returns a value of zero, PCI initialization is aborted; otherwise the controller structure is registered and initialization continues. -The default PCI target configuration is minimal -- it assumes that the -strapping registers are set as necessary. Since the strapping bits +The default 440GP PCI target configuration is minimal -- it assumes that +the strapping registers are set as necessary. Since the strapping bits provide very limited flexibility, you may want to customize the boards target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific code will call the routine pci_target_init() which you must implement @@ -136,7 +162,7 @@ in your board-specific code. Target initialization is completed by the cpu-specific code by initializing the subsystem id and subsystem vendor id, and then ensuring -that the enable host configuration bit in the PCIX0_BRDGOPT2 is set. +that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set. The default PCI master initialization maps in 256 MB of pci memory starting at PCI address CFG_PCI_MEMBASE. To customize this, define @@ -158,12 +184,13 @@ in a cPCI environment: 1. Arbiter strapping: Many cPCI boards provide an external arbiter (often part of the PCI-to-PCI bridge). Even though the arbiter is external (the arbiter strapping is negated), the CPU may still be required to perform -PCI bus configuration. +local PCI bus configuration. 2. Host only: PPMC boards must sample the MONARCH# signal at run-time. -Depending on the configuration of the carrier, the board must determine -if it should configure the PCI bus at run-time. In addition, access to -the MONARCH#signal is board-specific (e.g. via custom FPGA, etc). +Depending on the configuration of the carrier boar, the PPMC board must +determine if it should configure the PCI bus at run-time. And in most +cases, access to the MONARCH# signal is board-specific (e.g. via +board-specific FPGA registers, etc). In any event, the is_pci_host() routine gives each board the opportunity to decide at run-time. If your board is always configured a certain way, @@ -174,3 +201,4 @@ then just hardcode a return of 1 or 0 as appropriate. Regards, --Scott + diff --git a/include/configs/EBONY.h b/include/configs/EBONY.h index b97a1f2..aecb3c2 100644 --- a/include/configs/EBONY.h +++ b/include/configs/EBONY.h @@ -61,7 +61,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 192 kB for Mon */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ /*----------------------------------------------------------------------- @@ -103,6 +103,16 @@ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + + /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -163,11 +173,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - /*----------------------------------------------------------------------- * PCI stuff