From: Keith Busch Date: Thu, 13 Feb 2020 17:50:49 +0000 (-0800) Subject: Apply kernel-doc comments to more structs and enums X-Git-Tag: v1.0-rc0~175 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=135602b6a6101177a1b17b44b0292c2d81fffeee;p=users%2Fsagi%2Flibnvme.git Apply kernel-doc comments to more structs and enums Signed-off-by: Keith Busch --- diff --git a/src/nvme/types.h b/src/nvme/types.h index 34b3ebe3..1ce3f1d1 100644 --- a/src/nvme/types.h +++ b/src/nvme/types.h @@ -52,23 +52,33 @@ static inline uint64_t le64_to_cpu(__le64 x) } /** - * enum nvme_constants - - * @NVME_NSID_ALL: - * @NVME_NSID_NONE: - * @NVME_UUID_NONE: - * @NVME_CNTLID_NONE: - * @NVME_NVMSETID_NONE: - * @NVME_LOG_LSP_NONE: - * @NVME_LOG_LSI_NONE: - * @NVME_IDENTIFY_DATA_SIZE: - * @NVME_ID_NVMSET_LIST_MAX: - * @NVME_ID_UUID_LIST_MAX: - * @NVME_ID_CTRL_LIST_MAX: - * @NVME_ID_NS_LIST_MAX: - * @NVME_ID_SECONDARY_CTRL_MAX: - * @NVME_FEAT_LBA_RANGE_MAX: - * @NVME_LOG_ST_MAX_RESULTS: - * @NVME_DSM_MAX_RANGES: + * enum nvme_constants - A place to stash various constant nvme values + * @NVME_NSID_ALL: A broadcast value that is used to specify all + * namespaces + * @NVME_NSID_NONE: The invalid namespace id, for when the nsid + * parameter is not used in a command + * @NVME_UUID_NONE: Use to omit the uuid command parameter + * @NVME_CNTLID_NONE: Use to omit the cntlid command parameter + * @NVME_NVMSETID_NONE: Use to omit the nvmsetid command parameter + * @NVME_LOG_LSP_NONE: Use to omit the log lsp command parameter + * @NVME_LOG_LSI_NONE: Use to omit the log lsi command parameter + * @NVME_IDENTIFY_DATA_SIZE: The transfer size for nvme identify commands + * @NVME_ID_NVMSET_LIST_MAX: The largest possible nvmset index in identify + * nvmeset + * @NVME_ID_UUID_LIST_MAX: The largest possible uuid index in identify + * uuid list + * @NVME_ID_CTRL_LIST_MAX: The largest possible controller index in + * identify controller list + * @NVME_ID_NS_LIST_MAX: The largest possible namespace index in + * identify namespace list + * @NVME_ID_SECONDARY_CTRL_MAX: The largest possible secondary controller index + * in identify secondary controller + * @NVME_FEAT_LBA_RANGE_MAX: The largest possible LBA range index in feature + * lba range type + * @NVME_LOG_ST_MAX_RESULTS: The largest possible self test result index in the + * device self test log + * @NVME_DSM_MAX_RANGES: The largest possible range index in a data-set + * management command */ enum nvme_constants { NVME_NSID_ALL = 0xffffffff, @@ -91,11 +101,9 @@ enum nvme_constants { }; /** - * DOC: NVMe controller registers/properties - */ - -/** - * enum nvme_registers - + * enum nvme_registers - The nvme controller registers for all transports. This + * is the layout of BAR0/1 for PCIe, and properties for + * fabrics. * @NVME_REG_CAP: Controller Capabilities * @NVME_REG_VS: Version * @NVME_REG_INTMS: Interrupt Mask Set @@ -172,9 +180,6 @@ enum nvme_registers { #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) -/** - * enum - - */ enum { NVME_CC_ENABLE = 1 << 0, NVME_CC_CSS_NVM = 0 << 4, @@ -202,7 +207,7 @@ enum { NVME_CSTS_SHST_MASK = 3 << 2, }; -/* +/** * is_64bit_reg() - Checks if offset of the controller register is 64bit or not. * @offset: Offset of controller register field in bytes * @@ -227,24 +232,105 @@ static inline bool is_64bit_reg(__u32 offset) } /** - * DOC: NVMe Identify + * enum nvme_psd_flags - Possible flag values in nvme power state descriptor + * @NVME_PSD_FLAGS_MXPS: Indicates the scale for the Maximum Power + * field. If this bit is cleared, then the scale of the + * Maximum Power field is in 0.01 Watts. If this bit is + * set, then the scale of the Maximum Power field is in + * 0.0001 Watts. + * @NVME_PSD_FLAGS_NOPS: Indicates whether the controller processes I/O + * commands in this power state. If this bit is cleared, + * then the controller processes I/O commands in this + * power state. If this bit is set, then the controller + * does not process I/O commands in this power state. + */ +enum nvme_psd_flags { + NVME_PSD_FLAGS_MXPS = 1 << 0, + NVME_PSD_FLAGS_NOPS = 1 << 1, +}; + +/** + * enum nvme_psd_ps - Known values for &struct nvme_psd #ips and #aps. Use with + * nvme_psd_power_scale() to extract the power scale field + * to match this enum. + * NVME_PSD_IPS_100_MICRO_WATT: 0.0001 watt scale + * NVME_PSD_IPS_10_MILLI_WATT: 0.01 watt scale + */ +enum nvme_psd_ps { + NVME_PSD_PS_100_MICRO_WATT = 1, + NVME_PSD_PS_10_MILLI_WATT = 2, +}; + +/** + * nvme_psd_power_scale() - power scale occupies the upper 3 bits + */ +static inline unsigned nvme_psd_power_scale(__u8 ps) +{ + return ps >> 6; +} + +/** + * enum nvme_psd_workload - Specifies a workload hint in the Power Management + * Feature (see &struct nvme_psd.apw) to inform the + * NVM subsystem or indicate the conditions for the + * active power level. + * @NVME_PSD_WORKLOAD_1: Extended Idle Period with a Burst of Random Write + * consists of five minutes of idle followed by + * thirty-two random write commands of size 1 MiB + * submitted to a single controller while all other + * controllers in the NVM subsystem are idle, and then + * thirty (30) seconds of idle. + * @NVME_PSD_WORKLOAD_2: Heavy Sequential Writes consists of 80,000 + * sequential write commands of size 128 KiB submitted to + * a single controller while all other controllers in the + * NVM subsystem are idle. The submission queue(s) + * should be sufficiently large allowing the host to + * ensure there are multiple commands pending at all + * times during the workload. */ +enum nvme_psd_workload { + NVME_PSD_WORKLOAD_1 = 1, + NVME_PSD_WORKLOAD_2 = 2, +}; /** * struct nvme_id_psd - - * @mp: - * @flags: - * @enlat: - * @exlat: - * @rrt: - * @rrl: - * @rwt: - * @rwl: - * @idlp: - * @ips: - * @actp: - * @apw: - * @aps: + * @mp: Maximum Power indicates the sustained maximum power consumed by the + * NVM subsystem in this power state. The power in Watts is equal to + * the value in this field multiplied by the scale specified in the Max + * Power Scale bit (see &enum nvme_psd_flags). A value of 0 indicates + * Maximum Power is not reported. + * @flags: Additional decoding flags, see &enum nvme_psd_flags. + * @enlat: Entry Latency indicates the maximum latency in microseconds + * associated with entering this power state. A value of 0 indicates + * Entry Latency is not reported. + * @exlat: Exit Latency indicates the maximum latency in microseconds + * associated with exiting this power state. A value of 0 indicates + * Exit Latency is not reported. + * @rrt: Relative Read Throughput indicates the read throughput rank + * associated with this power state relative to others. The value in + * this is less than the number of supported power states. + * @rrl: Relative Reade Latency indicates the read latency rank associated + * with this power state relative to others. The value in this field is + * less than the number of supported power states. + * @rwt: Relative Write Throughput indicates write throughput rank associated + * with this power state relative to others. The value in this field is + * less than the number of supported power states + * @rwl: Relative Write Latency indicates the write latency rank associated + * with this power state relative to others. The value in this field is + * less than the number of supported power states + * @idlp: Idle Power indicates the typical power consumed by the NVM + * subsystem over 30 seconds in this power state when idle. + * @ips: Idle Power Scale indicates the scale for &struct nvme_id_psd.idlp, + * see &enum nvme_psd_ps for decoding this field. + * @actp: Active Power indicates the largest average power consumed by the + * NVM subsystem over a 10 second period in this power state with + * the workload indicated in the Active Power Workload field. + * @apw: Active Power Workload indicates the workload used to calculate + * maximum power for this power state. See &enum nvme_psd_workload for + * decoding this field. + * @aps: Active Power Scale indicates the scale for the &struct + * nvme_id_psd.actp, see &enum nvme_psd_ps for decoding this value. */ struct nvme_id_psd { __le16 mp; @@ -265,112 +351,194 @@ struct nvme_id_psd { __u8 rsvd23[8]; }; -/** - * nvme_psd_power_scale() - power scale occupies the upper 3 bits - */ -static inline unsigned nvme_psd_power_scale(__u8 ps) -{ - return ps >> 6; -} - -/** - * enum - - * @NVME_PSD_FLAGS_MAX_POWER_SCALE: - * @NVME_PSD_FLAGS_NON_OP_STATE: - * @NVME_PSD_RELATIVE_MASK: - * @NVME_PSD_APW_MASK: - */ -enum { - NVME_PSD_FLAGS_MAX_POWER_SCALE = 1 << 0, - NVME_PSD_FLAGS_NON_OP_STATE = 1 << 1, - NVME_PSD_RELATIVE_MASK = 0x1f, - NVME_PSD_APW_MASK = 0x7, -}; - /** * struct nvme_id_ctrl - Identify Controller data structure - * @vid: Vendor ID - * @ssvid: Subsystem Vendor Id - * @sn: Serial Number - * @mn: Model Number - * @fr: Firmware Revision - * @rab: Recommended Arbitration Burst - * @ieee: IEEE - * @cmic: Controller Mulitpathing Capabilities - * @mdts: Max Data Transfer Size - * @cntlid: Controller Identifier - * @ver: Version - * @rtd3r: Runtime D3 Resume - * @rtd3e: Runtime D3 Exit - * @oaes: Optional Async Events Supported - * @ctratt: Controller Attributes - * @rrls: Read Recovery Levels - * @cntrltype: Controller Type - * @fguid: FRU GUID - * @crdt1: Controller Retry Delay 1 - * @crdt2: Controller Retry Delay 2 - * @crdt3: Controller Retry Delay 3 - * @nvmsr: - * @vwci: - * @mec: - * @oacs: Optional Admin Commands Supported - * @acl: Abort Command Limit - * @aerl: Async Event Request Limit - * @frmw: - * @lpa: Log Page Attributes - * @elpe: - * @npss: Number of Power States Supported - * @avscc: - * @apsta: - * @wctemp: - * @cctemp: - * @mtfa: - * @hmpre: - * @hmmin: - * @tnvmcap: - * @unvmcap: - * @rpmbs: - * @edstt: - * @dsto: - * @fwug: - * @kas: - * @hctma: - * @mntmt: - * @mxtmt: - * @sanicap: - * @hmminds: - * @hmmaxd: - * @nsetidmax: - * @endgidmax: - * @anatt: - * @anacap: - * @anagrpmax: - * @nanagrpid: - * @pels: - * @sqes: - * @cqes: - * @maxcmd: - * @nn: - * @onc: - * @fuses: - * @fna: - * @vwc: - * @awun: - * @awupf: - * @nvscc: - * @nwpc: - * @acwu: - * @sgls: - * @mnan: - * @subnqn: - * @ioccsz: - * @iorcsz: - * @icdoff: - * @fcatt: - * @msdbd: - * @ofcs: - * @psd: - * @vs: + * @vid: PCI Vendor ID, the company vendor identifier that is assigned by + * the PCI SIG. + * @ssvid: PCI Subsystem Vendor ID, the company vendor identifier that is + * assigned by the PCI SIG for the subsystem. + * @sn: Serial Number in ascii + * @mn: Model Number in ascii + * @fr: Firmware Revision in ascii, the currently active firmware + * revision for the NVM subsystem + * @rab: Recommended Arbitration Burst, reported as a power of two + * @ieee: IEEE assigned Organization Unique Identifier + * @cmic: Controller Multipath IO and Namespace Sharing Capabilities of + * the controller and NVM subsystem. See &enum nvme_id_ctrl_cmic. + * @mdts: Max Data Transfer Size is the largest data transfer size. The + * host should not submit a command that exceeds this maximum data + * transfer size. The value is in units of the minimum memory page + * size (CAP.MPSMIN) and is reported as a power of two + * @cntlid: Controller ID, the NVM subsystem unique controller identifier + * associated with the controller. + * @ver: Version, this field contains the value reported in the Version + * register, or property (see &enum nvme_registers %NVME_REG_VS). + * @rtd3r: RTD3 Resume Latency, the expected latency in microseconds to resume + * from Runtime D3 + * @rtd3e: RTD3 Exit Latency, the typical latency in microseconds to enter + * Runtime D3. + * @oaes: Optional Async Events Supported, see @enum nvme_id_ctrl_oaes . + * @ctratt: Controller Attributes, see @enum nvme_id_ctrl_ctratt + * @rrls: Read Recovery Levels. If a bit is set, then the corresponding + * Read Recovery Level is supported. If a bit is cleared, then the + * corresponding Read Recovery Level is not supported. + * @cntrltype: Controller Type, see &enum nvme_id_ctrl_cntrltype + * @fguid: FRU GUID, a 128-bit value that is globally unique for a given + * Field Replaceable Unit + * @crdt1: Controller Retry Delay time in 100 millisecod units if CQE CRD + * field is 1 + * @crdt2: Controller Retry Delay time in 100 millisecod units if CQE CRD + * field is 2 + * @crdt3: Controller Retry Delay time in 100 millisecod units if CQE CRD + * field is 3 + * @nvmsr: NVM Subsystem Report, see &enum nvme_id_ctrl_nvmsr + * @vwci: VPD Write Cycle Information, see &enum nvme_id_ctrl_vwci + * @mec: Management Endpoint Capabilities, see &enum nvme_id_ctrl_mec + * @oacs: Optional Admin Command Support,the optional Admin commands and + * features supported by the controller, see &enum nvme_id_ctrl_oacs. + * @acl: Abort Command Limit, the maximum number of concurrently + * executing Abort commands supported by the controller. This is a + * 0's based value. + * @aerl: Async Event Request Limit, the maximum number of concurrently + * outstanding Asynchronous Event Request commands supported by the + * controller This is a 0's based value. + * @frmw: Firmware Updates indicates capabilities regarding firmware + * updates. See &enum nvme_id_ctrl_frmw. + * @lpa: Log Page Attributes, see &enum nvme_id_ctrl_lpa. + * @elpe: Error Log Page Entries, the maximum number of Error Information + * log entries that are stored by the controller. This field is a + * 0's based value. + * @npss: Number of Power States Supported, the number of NVM Express + * power states supported by the controller, indicating the number + * of valid entries in &struct nvme_id_ctrl.psd. This is a 0's + * based value. + * @avscc: Admin Vendor Specific Command Configuration, see &enum + * nvme_id_ctrl_avscc. + * @apsta: Autonomous Power State Transition Attributes, see &enum + * nvme_id_ctrl_apsta. + * @wctemp: Warning Composite Temperature Threshold indicates + * the minimum Composite Temperature field value (see &struct + * nvme_smart_log.critical_comp_time) that indicates an overheating + * condition during which controller operation continues. + * @cctemp: Critical Composite Temperature Threshold, field indicates the + * minimum Composite Temperature field value (see &struct +* nvme_smart_log.critical_comp_time) that indicates a critical + * overheating condition. + * @mtfa: Maximum Time for Firmware Activation indicates the maximum time + * the controller temporarily stops processing commands to activate + * the firmware image, specified in 100 millisecond units. This + * field is always valid if the controller supports firmware + * activation without a reset. + * @hmpre: Host Memory Buffer Preferred Size indicates the preferred size + * that the host is requested to allocate for the Host Memory + * Buffer feature in 4 KiB units. + * @hmmin: Host Memory Buffer Minimum Size indicates the minimum size that + * the host is requested to allocate for the Host Memory Buffer + * feature in 4 KiB units. + * @tnvmcap: Total NVM Capacity, the total NVM capacity in the NVM subsystem. + * The value is in bytes. + * @unvmcap: Unallocated NVM Capacity, the unallocated NVM capacity in the + * NVM subsystem. The value is in bytes. + * @rpmbs Replay Protected Memory Block Support, see &enum + * nvme_id_ctrl_rpmbs. + * @edstt Extended Device Self-test Time, if Device Self-test command is + * supported (see &struct nvme_id_ctrl.oacs, %NVME_CTRL_OACS_SELF_TEST), + * then this field indicates the nominal amount of time in one + * minute units that the controller takes to complete an extended + * device self-test operation when in power state 0. + * @dsto: Device Self-test Options, see &enum nvme_id_ctrl_dsto. + * @fwug: Firmware Update Granularity indicates the granularity and + * alignment requirement of the firmware image being updated by the + * Firmware Image Download command. The value is reported in 4 KiB + * units. A value of 0h indicates no information on granularity is + * provided. A value of FFh indicates no restriction + * @kas: Keep Alive Support indicates the granularity of the Keep Alive + * Timer in 100 millisecond units. + * @hctma: Host Controlled Thermal Management Attributes, see &enum nvme_id_ctrl_hctm. + * @mntmt: Minimum Thermal Management Temperature indicates the minimum + * temperature, in degrees Kelvin, that the host may request in the + * Thermal Management Temperature 1 field and Thermal Management + * Temperature 2 field of a Set Features command with the Feature + * Identifier field set to #NVME_FEAT_FID_HCTM. + * @mxtmt: Maximum Thermal Management Temperature indicates the maximum + * temperature, in degrees Kelvin, that the host may request in the + * Thermal Management Temperature 1 field and Thermal Management + * Temperature 2 field of the Set Features command with the Feature + * Identifier set to #NVME_FEAT_FID_HCTM. + * @sanicap: Sanitize Capabilities, see &enum nvme_id_ctrl_sanicap + * @hmminds: Host Memory Buffer Minimum Descriptor Entry Size indicates the + * minimum usable size of a Host Memory Buffer Descriptor Entry in + * 4 KiB units. + * @hmmaxd: Host Memory Maximum Descriptors Entries indicates the number of + * usable Host Memory Buffer Descriptor Entries. + * @nsetidmax: NVM Set Identifier Maximum, defines the maximum value of a valid + * NVM Set Identifier for any controller in the NVM subsystem. + * @endgidmax: Endurance Group Identifier Maximum, defines the maximum value of + * a valid Endurance Group Identifier for any controller in the NVM + * subsystem. + * @anatt: ANA Transition Time indicates the maximum amount of time, in + * seconds, for a transition between ANA states or the maximum + * amount of time, in seconds, that the controller reports the ANA + * change state. + * @anacap: Asymmetric Namespace Access Capabilities, see &enum + * nvme_id_ctrl_anacap. + * @anagrpmax: ANA Group Identifier Maximum indicates the maximum value of a + * valid ANA Group Identifier for any controller in the NVM + * subsystem. + * @nanagrpid: Number of ANA Group Identifiers indicates the number of ANA + * groups supported by this controller. + * @pels: Persistent Event Log Size indicates the maximum reportable size + * for the Persistent Event Log. + * @sqes: Submission Queue Entry Size, see &enum nvme_id_ctrl_sqes. + * @cqes: Completion Queue Entry Size, see &enum nvme_id_ctrl_cqes. + * @maxcmd: Maximum Outstanding Commands indicates the maximum number of + * commands that the controller processes at one time for a + * particular queue. + * @nn: Number of Namespaces indicates the maximum value of a valid + * nsid for the NVM subsystem. If the MNAN (&struct nvme_id_ctrl.mnan + * field is cleared to 0h, then this field also indicates the + * maximum number of namespaces supported by the NVM. subsystem. + * @oncs: Optional NVM Command Support, see &enum nvme_id_ctrl_oncs. + * @fuses: Fused Operation Support, see &enum nvme_id_ctrl_fuses. + * @fna: Format NVM Attributes, see &enum nvme_id_ctrl_fna. + * @vwc: Volatile Write Cache, see &enum nvme_id_ctrl_vwc. + * @awun: Atomic Write Unit Normal indicates the size of the write + * operation guaranteed to be written atomically to the NVM across + * all namespaces with any supported namespace format during normal + * operation. This field is specified in logical blocks and is a + * 0's based value. + * @awupf: Atomic Write Unit Power Fail indicates the size of the write + * operation guaranteed to be written atomically to the NVM across + * all namespaces with any supported namespace format during a + * power fail or error condition. This field is specified in + * logical blocks and is a 0’s based value. + * @nvscc: NVM Vendor Specific Command Configuration, see &enum + * nvme_id_ctrl_nvscc. + * @nwpc: Namespace Write Protection Capabilities, see &enum + * nvme_id_ctrl_nwpc. + * @acwu: Atomic Compare & Write Unit indicates the size of the write + * operation guaranteed to be written atomically to the NVM across + * all namespaces with any supported namespace format for a Compare + * and Write fused operation. This field is specified in logical + * blocks and is a 0’s based value. + * @sgls: SGL Support, see &enum nvme_id_ctrl_sgls + * @mnan: Maximum Number of Allowed Namespaces indicates the maximum + * number of namespaces supported by the NVM subsystem. + * @subnqn: NVM Subsystem NVMe Qualified Name, UTF-8 null terminated string + * @ioccsz: I/O Queue Command Capsule Supported Size, defines the maximum + * I/O command capsule size in 16 byte units. + * @iorcsz: I/O Queue Response Capsule Supported Size, defines the maximum + * I/O response capsule size in 16 byte units. + * @icdoff: In Capsule Data Offset, defines the offset where data starts + * within a capsule. This value is applicable to I/O Queues only. + * @fcatt: Fabrics Controller Attributes, see &enum nvme_id_ctrl_fcatt. + * @msdbd: Maximum SGL Data Block Descriptors indicates the maximum + * number of SGL Data Block or Keyed SGL Data Block descriptors + * that a host is allowed to place in a capsule. A value of 0h + * indicates no limit. + * @ofcs: Optional Fabric Commands Support, see &enum nvme_id_ctrl_ofcs. + * @psd: Power State Descriptors, see &struct nvme_id_psd. + * @vs: Vendor Specific */ struct nvme_id_ctrl { __le16 vid; @@ -468,9 +636,13 @@ struct nvme_id_ctrl { }; /** - * enum - + * enum nvme_id_ctrl_cmic - + * @NVME_CTRL_CMIC_MULTI_PORT: + * @NVME_CTRL_CMIC_MULTI_CTRL: + * @NVME_CTRL_CMIC_MULTI_SRIOV: + * @NVME_CTRL_CMIC_MULTI_ANA_REPORTING: */ -enum { +enum nvme_id_ctrl_cmic { NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, NVME_CTRL_CMIC_MULTI_SRIOV = 1 << 2, @@ -478,9 +650,15 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_oaes - The typical latency in microseconds to enter Runtime D3 + * @NVME_CTRL_OAES_NA: + * @NVME_CTRL_OAES_FA: + * @NVME_CTRL_OAES_ANA: + * @NVME_CTRL_OAES_PLEA: + * @NVME_CTRL_OAES_LBAS:: + * @NVME_CTRL_OAES_EGE: */ -enum { +enum nvme_id_ctrl_oaes { NVME_CTRL_OAES_NA = 1 << 8, NVME_CTRL_OAES_FA = 1 << 9, NVME_CTRL_OAES_ANA = 1 << 11, @@ -490,9 +668,19 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_ctratt - + * @NVME_CTRL_CTRATT_128_ID: + * @NVME_CTRL_CTRATT_NON_OP_PSP: + * @NVME_CTRL_CTRATT_NVM_SETS: + * @NVME_CTRL_CTRATT_READ_RECV_LVLS: + * @NVME_CTRL_CTRATT_ENDURANCE_GROUPS: + * @NVME_CTRL_CTRATT_PREDICTABLE_LAT: + * @NVME_CTRL_CTRATT_TBKAS: + * @NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY: + * @NVME_CTRL_CTRATT_SQ_ASSOCIATIONS: + * @NVME_CTRL_CTRATT_UUID_LIST: */ -enum { +enum nvme_id_ctrl_ctratt { NVME_CTRL_CTRATT_128_ID = 1 << 0, NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, @@ -506,43 +694,95 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_cntrltype - + * @NVME_CTRL_CNTRLTYPE_IO: + * @NVME_CTRL_CNTRLTYPE_DISCOVERY: + * @NVME_CTRL_CNTRLTYPE_ADMIN: */ -enum { - NVME_CTRL_CNTRLTYPE_RESERVED = 0, +enum nvme_id_ctrl_cntrltype { NVME_CTRL_CNTRLTYPE_IO = 1, NVME_CTRL_CNTRLTYPE_DISCOVERY = 2, NVME_CTRL_CNTRLTYPE_ADMIN = 3, }; /** - * enum - + * enum nvme_id_ctrl_nvmsr - This field reports information associated with the + * NVM Subsystem, see &struct nvme_id_ctrl.nvmsr. + * @NVME_CTRL_NVMSR_NVMESD: If set, then the NVM Subsystem is part of an NVMe + * Storage Device; if cleared, then the NVM Subsystem + * is not part of an NVMe Storage Device. + * @NVME_CTRL_NVMSR_NVMEE: If set’, then the NVM Subsystem is part of an NVMe + * Enclosure; if cleared, then the NVM Subsystem is + * not part of an NVMe Enclosure. */ -enum { +enum nvme_id_ctrl_nvmsr { NVME_CTRL_NVMSR_NVMESD = 1 << 0, NVME_CTRL_NVMSR_NVMEE = 1 << 1, }; /** - * enum - - */ -enum { + * enum nvme_id_ctrl_vwci - This field indicates information about remaining + * number of times that VPD contents are able to be + * updated using the VPD Write command, see &struct + * nvme_id_ctrl.vwci. + * @NVME_CTRL_VWCI_VWCR: Mask to get value of VPD Write Cycles Remaining. If + * the VPD Write Cycle Remaining Valid bit is set, then + * this field contains a value indicating the remaining + * number of times that VPD contents are able to be + * updated using the VPD Write command. If this field is + * set to 7Fh, then the remaining number of times that + * VPD contents are able to be updated using the VPD + * Write command is greater than or equal to 7Fh. + * @NVME_CTRL_VWCI_VWCRV: VPD Write Cycle Remaining Valid. If this bit is set, + * then the VPD Write Cycle Remaining field is valid. If + * this bit is cleared, then the VPD Write Cycles + * Remaining field is invalid and cleared to 0h. + */ +enum nvme_id_ctrl_vwci { NVME_CTRL_VWCI_VWCR = 0x7f << 0, NVME_CTRL_VWCI_VWCRV = 1 << 7, }; /** - * enum - + * enum nvme_id_ctrl_mec - Flags indicatings the capabilities of the Management + * Endpoint in the Controller, &struct nvme_id_ctrl.mec. + * @NVME_CTRL_MEC_SMBUSME: If set, then the NVM Subsystem contains a Management + * Endpoint on an SMBus/I2C port. + * @NVME_CTRL_MEC_PCIEME: If set, then the NVM Subsystem contains a Management + * Endpoint on a PCIe port. */ -enum { +enum nvme_id_ctrl_mec { NVME_CTRL_MEC_SMBUSME = 1 << 0, NVME_CTRL_MEC_PCIEME = 1 << 1, }; /** - * enum - - */ -enum { + * enum nvme_id_ctrl_oacs - Flags indicating the optional Admin commands and + * features supported by the controller, see + * &struct nvme_id_ctrl.oacs. + * @NVME_CTRL_OACS_SECURITY: If set, then the controller supports the + * Security Send and Security Receive commands. + * @NVME_CTRL_OACS_FORMAT: If set then the controller supports the Format + * NVM command. + * @NVME_CTRL_OACS_FW: If set, then the controller supports the + * Firmware Commit and Firmware Image Download commands. + * @NVME_CTRL_OACS_NS_MGMT: If set, then the controller supports the + * Namespace Management capability + * @NVME_CTRL_OACS_SELF_TEST: If set, then the controller supports the Device + * Self-test command. + * @NVME_CTRL_OACS_DIRECTIVES: If set, then the controller supports Directives + * and the Directive Send and Directive Receive + * commands. + * @NVME_CTRL_OACS_NVME_MI: If set, then the controller supports the NVMe-MI + * Send and NVMe-MI Receive commands. + * @NVME_CTRL_OACS_VIRT_MGMT: If set, then the controller supports the + * Virtualization Management command. + * @NVME_CTRL_OACS_DBBUF_CFG: If set, then the controller supports the + * Doorbell Buffer Config command. + * @NVME_CTRL_OACS_LBA_STATUS: If set, then the controller supports the Get LBA + * Status capability. + */ +enum nvme_id_ctrl_oacs { NVME_CTRL_OACS_SECURITY = 1 << 0, NVME_CTRL_OACS_FORMAT = 1 << 1, NVME_CTRL_OACS_FW = 1 << 2, @@ -556,18 +796,30 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_frmw - Flags and values indicates capabilities regarding + * firmware updates from &struct nvme_id_ctrl.frmw. + * @NVME_CTRL_FRMW_1ST_RO: If set, the first firmware slot is readonly + * @NVME_CTRL_FRMW_NR_SLOTS: Mask to get the value of the number of + * firmware slots that the controller supports. + * @NVME_CTRL_FRMW_FW_ACT_NO_RESET: If set, the controller supports firmware + * activation without a reset. */ -enum { +enum nvme_id_ctrl_frmw { NVME_CTRL_FRMW_1ST_RO = 1 << 0, NVME_CTRL_FRMW_NR_SLOTS = 3 << 1, NVME_CTRL_FRMW_FW_ACT_NO_RESET = 1 << 4, }; /** - * enum - + * enum nvme_id_ctrl_lpa - Flags indicating optional attributes for log pages + * that are accessed via the Get Log Page command. + * @NVME_CTRL_LPA_SMART_PER_NS: + * @NVME_CTRL_LPA_CMD_EFFECTS: + * @NVME_CTRL_LPA_EXTENDED: + * @NVME_CTRL_LPA_TELEMETRY: + * @NVME_CTRL_LPA_PERSETENT_EVENT: */ -enum { +enum nvme_id_ctrl_lpa { NVME_CTRL_LPA_SMART_PER_NS = 1 << 0, NVME_CTRL_LPA_CMD_EFFECTS = 1 << 1, NVME_CTRL_LPA_EXTENDED = 1 << 2, @@ -576,47 +828,82 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_avscc - Flags indicating the configuration settings for + * Admin Vendor Specific command handling. + * @NVME_CTRL_AVSCC_AVS: If set, all Admin Vendor Specific Commands use the + * optional vendor specific command format with NDT and + * NDM fields. */ -enum { +enum nvme_id_ctrl_avscc { NVME_CTRL_AVSCC_AVS = 1 << 0, }; /** - * enum - + * enum nvme_id_ctrl_apsta - Flags indicating the attributes of the autonomous + * power state transition feature. + * @NVME_CTRL_APSTA_APST: If set, then the controller supports autonomous power + * state transitions. */ -enum { +enum nvme_id_ctrl_apsta { NVME_CTRL_APSTA_APST = 1 << 0, }; /** - * enum - + * enum nvme_id_ctrl_rpmbs - This field indicates if the controller supports + * one or more Replay Protected Memory Blocks, from + * &struct nvme_id_ctrl.rpmbs. + * @NVME_CTRL_RPMBS_NR_UNITS: Mask to get the value of the Number of RPMB Units + * @NVME_CTRL_RPMBS_AUTH_METHOD: Mask to get the value of the Authentication Method + * @NVME_CTRL_RPMBS_TOTAL_SIZE: Mask to get the value of Total Size + * @NVME_CTRL_RPMBS_ACCESS_SIZE: Mask to get the value of Access Size */ -enum { +enum nvme_id_ctrl_rpmbs { NVME_CTRL_RPMBS_NR_UNITS = 7 << 0, NVME_CTRL_RPMBS_AUTH_METHOD = 7 << 3, - NVME_CTRL_RPMBS_TOTAL_SIZE = 255 << 16, - NVME_CTRL_RPMBS_ACCESS_SIZE = 255 << 24, + NVME_CTRL_RPMBS_TOTAL_SIZE = 0xff << 16, + NVME_CTRL_RPMBS_ACCESS_SIZE = 0xff << 24, }; /** - * enum - + * enum nvme_id_ctrl_dsto - Flags indicating the optional Device Self-test + * command or operation behaviors supported by the + * controller or NVM subsystem. + * @NVME_CTRL_DSTO_ONE_DST: If set, then the NVM subsystem supports only one + * device self-test operation in progress at a time. */ -enum { +enum nvme_id_ctrl_dsto { NVME_CTRL_DSTO_ONE_DST = 1 << 0, }; /** - * enum - + * enum nvme_id_ctrl_hctm - Flags indicate the attributes of the host + * controlled thermal management feature + * @NVME_CTRL_HCTMA_HCTM: then the controller supports host controlled thermal + * management, and the Set Features command and Get + * Features command with the Feature Identifier field + * set to %NVME_FEAT_FID_HCTM. */ -enum { +enum nvme_id_ctrl_hctm { NVME_CTRL_HCTMA_HCTM = 1 << 0, }; /** - * enum - + * enum nvme_id_ctrl_sanicap - Indicates attributes for sanitize operations. + * @NVME_CTRL_SANICAP_CES: Crypto Erase Support. If set, then the + * controller supports the Crypto Erase sanitize operation. + * @NVME_CTRL_SANICAP_BES: Block Erase Support. If set, then the controller + * supports the Block Erase sanitize operation. + * @NVME_CTRL_SANICAP_OWS: Overwrite Support. If set, then the controller + * supports the Overwrite sanitize operation. + * @NVME_CTRL_SANICAP_NDI: No-Deallocate Inhibited. If set and the No- + * Deallocate Response Mode bit is set, then the + * controller deallocates after the sanitize + * operation even if the No-Deallocate After + * Sanitize bit is set in a Sanitize command. + * @NVME_CTRL_SANICAP_NODMMAS: No-Deallocate Modifies Media After Sanitize, + * mask to extract value. */ -enum { +enum nvme_id_ctrl_sanicap { NVME_CTRL_SANICAP_CES = 1 << 0, NVME_CTRL_SANICAP_BES = 1 << 1, NVME_CTRL_SANICAP_OWS = 1 << 2, @@ -625,9 +912,28 @@ enum { }; /** - * enum - - */ -enum { + * enum nvme_id_ctrl_anacap - This field indicates the capabilities associated + * with Asymmetric Namespace Access Reporting. + * @NVME_CTRL_ANACAP_OPT: If set, then the controller is able to + * report ANA Optimized state. + * @NVME_CTRL_ANACAP_NON_OPT: If set, then the controller is able to + * report ANA Non-Optimized state. + * @NVME_CTRL_ANACAP_INACCESSIBLE: If set, then the controller is able to + * report ANA Inaccessible state. + * @NVME_CTRL_ANACAP_PERSISTENT_LOSS: If set, then the controller is able to + * report ANA Persistent Loss state. + * @NVME_CTRL_ANACAP_CHANGE: If set, then the controller is able to + * report ANA Change state. + * @NVME_CTRL_ANACAP_GRPID_NO_CHG: If set, then the ANAGRPID field in the + * Identify Namespace data structure + * (&struct nvme_id_ns.anagrpid), does not + * change while the namespace is attached to + * any controller. + * @NVME_CTRL_ANACAP_GRPID_MGMT: If set, then the controller supports a + * non-zero value in the ANAGRPID field of + * the Namespace Management command. + */ +enum nvme_id_ctrl_anacap { NVME_CTRL_ANACAP_OPT = 1 << 0, NVME_CTRL_ANACAP_NON_OPT = 1 << 1, NVME_CTRL_ANACAP_INACCESSIBLE = 1 << 2, @@ -638,25 +944,55 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_sqes - Defines the required and maximum Submission Queue + * entry size when using the NVM Command Set. + * @NVME_CTRL_SQES_MIN: Mask to get the value of the required Submission Queue + * Entry size when using the NVM Command Set. + * @NVME_CTRL_SQES_MAX: Mask to get the value of the maximum Submission Queue + * entry size when using the NVM Command Set. */ -enum { - NVME_CTRL_SQES_MIN = 15 << 0, - NVME_CTRL_SQES_MAX = 15 << 4, +enum nvme_id_ctrl_sqes { + NVME_CTRL_SQES_MIN = 0xf << 0, + NVME_CTRL_SQES_MAX = 0xf << 4, }; /** - * enum - + * enum nvme_id_ctrl_cqes - Defines the required and maximum Completion Queue + * entry size when using the NVM Command Set. + * @NVME_CTRL_CQES_MIN: Mask to get the value of the required Completion Queue + * Entry size when using the NVM Command Set. + * @NVME_CTRL_CQES_MAX: Mask to get the value of the maximum Completion Queue + * entry size when using the NVM Command Set. */ enum { - NVME_CTRL_CQES_MIN = 15 << 0, - NVME_CTRL_CQES_MAX = 15 << 4, + NVME_CTRL_CQES_MIN = 0xf << 0, + NVME_CTRL_CQES_MAX = 0xf << 4, }; /** - * enum - + * enum nvme_id_ctrl_oncs - This field indicates the optional NVM commands and + * features supported by the controller. + * @NVME_CTRL_ONCS_COMPARE: If set, then the controller supports + * the Compare command. + * @NVME_CTRL_ONCS_WRITE_UNCORRECTABLE: If set, then the controller supports + * the Write Uncorrectable command. + * @NVME_CTRL_ONCS_DSM: If set, then the controller supports + * the Dataset Management command. + * @NVME_CTRL_ONCS_WRITE_ZEROES: If set, then the controller supports + * the Write Zeroes command. + * @NVME_CTRL_ONCS_SAVE_FEATURES: If set, then the controller supports + * the Save field set to a non-zero value + * in the Set Features command and the + * Select field set to a non-zero value in + * the Get Features command. + * @NVME_CTRL_ONCS_RESERVATIONS: If set, then the controller supports + * reservations. + * @NVME_CTRL_ONCS_TIMESTAMP: If set, then the controller supports + * the Timestamp feature. + * @NVME_CTRL_ONCS_VERIFY: If set, then the controller supports + * the Verify command. */ -enum { +enum nvme_id_ctrl_oncs { NVME_CTRL_ONCS_COMPARE = 1 << 0, NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, NVME_CTRL_ONCS_DSM = 1 << 2, @@ -668,49 +1004,105 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_fuses - This field indicates the fused operations that the + * controller supports. + * @NVME_CTRL_FUSES_COMPARE_AND_WRITE: If set, then the controller supports the + * Compare and Write fused operation. */ -enum { +enum nvme_id_ctrl_fuses { NVME_CTRL_FUSES_COMPARE_AND_WRITE = 1 << 0, }; /** - * enum - - */ -enum { + * enum nvme_id_ctrl_fna - This field indicates attributes for the Format NVM + * command. + * @NVME_CTRL_FNA_FMT_ALL_NAMESPACES: If set, then all namespaces in an NVM + * subsystem shall be configured with the + * same attributes and a format (excluding + * secure erase) of any namespace results in + * a format of all namespaces in an NVM + * subsystem. If cleared, then the + * controller supports format on a per + * namespace basis. + * @NVME_CTRL_FNA_SEC_ALL_NAMESPACES: If set, then any secure erase performed + * as part of a format operation results in + * a secure erase of all namespaces in the + * NVM subsystem. If cleared, then any + * secure erase performed as part of a + * format results in a secure erase of the + * particular namespace specified. + * @NVME_CTRL_FNA_CRYPTO_ERASE: If set, then cryptographic erase is + * supported. If cleared, then cryptographic + * erase is not supported. + */ +enum nvme_id_ctrl_fna { NVME_CTRL_FNA_FMT_ALL_NAMESPACES = 1 << 0, NVME_CTRL_FNA_SEC_ALL_NAMESPACES = 1 << 1, NVME_CTRL_FNA_CRYPTO_ERASE = 1 << 2, }; /** - * enum - + * enum nvme_id_ctrl_vwc - + * @NVME_CTRL_VWC_PRESENT: If set, indicates a volatile write cache is present. + * If a volatile write cache is present, then the host + * controls whether the volatile write cache is enabled + * with a Set Features command specifying the value + * %NVME_FEAT_FID_VOLATILE_WC. + * @NVME_CTRL_VWC_FLUSH: Mask to get the value of the flush command behavior. */ -enum { +enum nvme_id_ctrl_vwc { NVME_CTRL_VWC_PRESENT = 1 << 0, NVME_CTRL_VWC_FLUSH = 3 << 1, }; /** - * enum - + * enum nvme_id_ctrl_nvscc - This field indicates the configuration settings + * for NVM Vendor Specific command handling. + * @NVME_CTRL_NVSCC_FMT: If set, all NVM Vendor Specific Commands use the + * format format with NDT and NDM fields. */ -enum { +enum nvme_id_ctrl_nvscc { NVME_CTRL_NVSCC_FMT = 1 << 0, }; /** - * enum - - */ -enum { + * enum nvme_id_ctrl_nwpc - This field indicates the optional namespace write + * protection capabilities supported by the + * controller. + * @NVME_CTRL_NWPC_WRITE_PROTECT: If set, then the controller shall + * support the No Write Protect and + * Write Protect namespace write + * protection states and may support + * the Write Protect Until Power + * Cycle state and Permanent Write + * Protect namespace write + * protection states. + * @NVME_CTRL_NWPC_WRITE_PROTECT_POWER_CYCLE: If set, then the controller + * supports the Write Protect Until + * Power Cycle state. + * @NVME_CTRL_NWPC_WRITE_PROTECT_PERMANENT: If set, then the controller + * supports the Permanent Write + * Protect state. + */ +enum nvme_id_ctrl_nwpc { NVME_CTRL_NWPC_WRITE_PROTECT = 1 << 0, NVME_CTRL_NWPC_WRITE_PROTECT_POWER_CYCLE= 1 << 1, NVME_CTRL_NWPC_WRITE_PROTECT_PERMANENT = 1 << 2, }; /** - * enum - + * enum nvme_id_ctrl_sgls - This field indicates if SGLs are supported for the + * NVM Command Set and the particular SGL types supported. + * @NVME_CTRL_SGLS_SUPPORTED: + * @NVME_CTRL_SGLS_KEYED: + * @NVME_CTRL_SGLS_BIT_BUCKET: + * @NVME_CTRL_SGLS_MPTR_BYTE_ALIGNED: + * @NVME_CTRL_SGLS_OVERSIZE: + * @NVME_CTRL_SGLS_MPTR_SGL: + * @NVME_CTRL_SGLS_OFFSET: + * @NVME_CTRL_SGLS_TPORT: */ -enum { +enum nvme_id_ctrl_sgls { NVME_CTRL_SGLS_SUPPORTED = 3 << 0, NVME_CTRL_SGLS_KEYED = 1 << 2, NVME_CTRL_SGLS_BIT_BUCKET = 1 << 16, @@ -722,24 +1114,34 @@ enum { }; /** - * enum - + * enum nvme_id_ctrl_fcatt - This field indicates attributes of the controller + * that are specific to NVMe over Fabrics. + * @NVME_CTRL_FCATT_DYNAMIC: If cleared, then the NVM subsystem uses a dynamic + * controller model. If set, then the NVM subsystem + * uses a static controller model. */ -enum { +enum nvme_id_ctrl_fcatt { NVME_CTRL_FCATT_DYNAMIC = 1 << 0, }; /** - * enum - + * enum nvme_id_ctrl_ofcs - Indicate whether the controller supports optional + * fabric commands. + * @NVME_CTRL_OFCS_DISCONNECT: If set, then the controller supports the + * Disconnect command and deletion of individual + * I/O Queues. */ -enum { +enum nvme_id_ctrl_ofcs { NVME_CTRL_OFCS_DISCONNECT = 1 << 0, }; /** - * struct nvme_lbaf - - * @ms: - * @ds: - * @rp: + * struct nvme_lbaf - LBA Format Data Structure + * @ms: Metadata Size indicates the number of metadata bytes provided per LBA + * based on the LBA Data Size indicated. + * @ds: LBA Data Size indicates the LBA data size supported, reported as a + * power of two. + * @rp: Relative Performance, see &enum nvme_lbaf_rp. */ struct nvme_lbaf { __le16 ms; @@ -748,13 +1150,17 @@ struct nvme_lbaf { }; /** - * enum - - * @NVME_LBAF_RP_BEST: - * @NVME_LBAF_RP_BETTER: - * @NVME_LBAF_RP_GOOD: - * @NVME_LBAF_RP_DEGRADED: + * enum nvme_lbaf_rp - This field indicates the relative performance of the LBA + * format indicated relative to other LBA formats supported + * by the controller. + * @NVME_LBAF_RP_BEST: Best performance + * @NVME_LBAF_RP_BETTER: Better performance + * @NVME_LBAF_RP_GOOD: Good performance + * @NVME_LBAF_RP_DEGRADED: Degraded performance + * @NVME_LBAF_RP_MASK: Mask to get the relative performance value from the + * field */ -enum { +enum nvme_lbaf_rp { NVME_LBAF_RP_BEST = 0, NVME_LBAF_RP_BETTER = 1, NVME_LBAF_RP_GOOD = 2, @@ -763,41 +1169,91 @@ enum { }; /** - * struct nvme_id_ns - - * @nsze: - * @ncap: - * @nuse: - * @nsfeat: - * @nlbaf: - * @flbas: - * @mc: - * @dpc: - * @dps: - * @nmic: - * @rescap: - * @fpi: - * @dlfeat: - * @nawun: - * @nawupf: - * @nacwu: - * @nabsn: - * @nabo: - * @nabspf: - * @noiob: - * @nvmcap: - * @npwg: - * @npwa: - * @npdg: - * @npda: - * @nows: - * @anagrpid: - * @nsattr: - * @nvmsetid: - * @endgid: - * @nguid: - * @eui64: - * @lbaf: - * @vs: + * struct nvme_id_ns - Identify Namespace data structure + * @nsze: Namespace Size indicates the total size of the namespace in + * logical blocks. The number of logical blocks is based on the + * formatted LBA size. + * @ncap: Namespace Capacity indicates the maximum number of logical blocks + * that may be allocated in the namespace at any point in time. The + * number of logical blocks is based on the formatted LBA size. + * @nuse: Namespace Utilization indicates the current number of logical + * blocks allocated in the namespace. This field is smaller than or + * equal to the Namespace Capacity. The number of logical blocks is + * based on the formatted LBA size. + * @nsfeat: Namespace Features, see &enum nvme_id_nsfeat. + * @nlbaf: Number of LBA Formats defines the number of supported LBA data + * size and metadata size combinations supported by the namespace + * and the highest possible index to &struct nvme_id_ns.labf. + * @flbas: Formatted LBA Size, see &enum nvme_id_ns_flbas. + * @mc: Metadata Capabilities, see &enum nvme_id_ns_mc. + * @dpc: End-to-end Data Protection Capabilities, see &enum + * nvme_id_ns_dpc. + * @dps: End-to-end Data Protection Type Settings, see &enum + * nvme_id_ns_dps. + * @nmic: Namespace Multi-path I/O and Namespace Sharing Capabilities, see + * &enum nvme_id_ns_nmic. + * @rescap: Reservation Capabilities, see &enum nvme_id_ns_rescap. + * @fpi: Format Progress Indicator, see &enum nvme_nd_ns_fpi. + * @dlfeat: Deallocate Logical Block Features, see &enum nvme_id_ns_dlfeat. + * @nawun: Namespace Atomic Write Unit Normal indicates the + * namespace specific size of the write operation guaranteed to be + * written atomically to the NVM during normal operation. + * @nawupf: Namespace Atomic Write Unit Power Fail indicates the + * namespace specific size of the write operation guaranteed to be + * written atomically to the NVM during a power fail or error + * condition. + * @nacwu: Namespace Atomic Compare & Write Unit indicates the namespace + * specific size of the write operation guaranteed to be written + * atomically to the NVM for a Compare and Write fused command. + * @nabsn: Namespace Atomic Boundary Size Normal indicates the atomic + * boundary size for this namespace for the NAWUN value. This field + * is specified in logical blocks. + * @nabo: Namespace Atomic Boundary Offset indicates the LBA on this + * namespace where the first atomic boundary starts. + * @nabspf: Namespace Atomic Boundary Size Power Fail indicates the atomic + * boundary size for this namespace specific to the Namespace Atomic + * Write Unit Power Fail value. This field is specified in logical + * blocks. + * @noiob: Namespace Optimal I/O Boundary indicates the optimal I/O boundary + * for this namespace. This field is specified in logical blocks. + * The host should construct Read and Write commands that do not + * cross the I/O boundary to achieve optimal performance. + * @nvmcap: NVM Capacity indicates the total size of the NVM allocated to + * this namespace. The value is in bytes. + * @npwg: Namespace Preferred Write Granularity indicates the smallest + * recommended write granularity in logical blocks for this + * namespace. This is a 0's based value. + * @npwa: Namespace Preferred Write Alignment indicates the recommended + * write alignment in logical blocks for this namespace. This is a + * 0's based value. + * @npdg: Namespace Preferred Deallocate Granularity indicates the + * recommended granularity in logical blocks for the Dataset + * Management command with the Attribute - Deallocate bit. + * @npda: Namespace Preferred Deallocate Alignment indicates the + * recommended alignment in logical blocks for the Dataset + * Management command with the Attribute - Deallocate bit + * @nows: Namespace Optimal Write Size indicates the size in logical blocks + * for optimal write performance for this namespace. This is a 0's + * based value. + * @anagrpid: ANA Group Identifier indicates the ANA Group Identifier of the + * ANA group of which the namespace is a member. + * @nsattr: Namespace Attributes, see &enum nvme_id_ns_attr. + * @nvmsetid: NVM Set Identifier indicates the NVM Set with which this + * namespace is associated. + * @endgid: Endurance Group Identifier indicates the Endurance Group with + * which this namespace is associated. + * @nguid: Namespace Globally Unique Identifier contains a 128-bit value + * that is globally unique and assigned to the namespace when the + * namespace is created. This field remains fixed throughout the + * life of the namespace and is preserved across namespace and + * controller operations + * @eui64: IEEE Extended Unique Identifier contains a 64-bit IEEE Extended + * Unique Identifier (EUI-64) that is globally unique and assigned + * to the namespace when the namespace is created. This field + * remains fixed throughout the life of the namespace and is + * preserved across namespace and controller operations + * @lbaf: LBA Format, see &struct nvme_lbaf. + * @vs: Vendor Specific */ struct nvme_id_ns { __le64 nsze; @@ -840,9 +1296,28 @@ struct nvme_id_ns { }; /** - * enum - - */ -enum { + * enum nvme_id_nsfeat - This field defines features of the namespace. + * @NVME_NS_FEAT_THIN: If set, indicates that the namespace supports thin + * provisioning. Specifically, the Namespace Capacity + * reported may be less than the Namespace Size. + * @NVME_NS_FEAT_NATOMIC: If set, indicates that the fields NAWUN, NAWUPF, and + * NACWU are defined for this namespace and should be + * used by the host for this namespace instead of the + * AWUN, AWUPF, and ACWU fields in the Identify + * Controller data structure. + * @NVME_NS_FEAT_DULBE: If set, indicates that the controller supports the + * Deallocated or Unwritten Logical Block error for + * this namespace. @NVME_NS_FEAT_ID_REUSE: If set, + * indicates that the value in the NGUID field for this + * namespace, if non- zero, is never reused by the + * controller and that the value in the EUI64 field for + * this namespace, if non-zero, is never reused by the + * controller. + * @NVME_NS_FEAT_IO_OPT: If set, indicates that the fields NPWG, NPWA, NPDG, + * NPDA, and NOWS are defined for this namespace and + * should be used by the host for I/O optimization + */ +enum nvme_id_nsfeat { NVME_NS_FEAT_THIN = 1 << 0, NVME_NS_FEAT_NATOMIC = 1 << 1, NVME_NS_FEAT_DULBE = 1 << 2, @@ -851,25 +1326,53 @@ enum { }; /** - * enum - + * enum nvme_id_ns_flbas - This field indicates the LBA data size & metadata + * size combination that the namespace has been + * formatted with + * @NVME_NS_FLBAS_LBA_MASK: Mask to get the index of one of the 16 supported + * LBA Formats indicated in &struct nvme_id_ns.lbaf. + * @NVME_NS_FLBAS_META_EXT: Applicable only if format contains metadata. If + * this bit is set, indicates that the metadata is + * transferred at the end of the data LBA, creating an + * extended data LBA. If cleared, indicates that all + * of the metadata for a command is transferred as a + * separate contiguous buffer of data. */ -enum { +enum nvme_id_ns_flbas { NVME_NS_FLBAS_LBA_MASK = 15 << 0, NVME_NS_FLBAS_META_EXT = 1 << 4, }; /** - * enum - + * enum nvme_id_ns_mc - This field indicates the capabilities for metadata. + * @NVME_NS_MC_EXTENDED: If set, indicates the namespace supports the metadata + * being transferred as part of a separate buffer that is + * specified in the Metadata Pointer. + * @NVME_NS_MC_SEPARATE: If set, indicates that the namespace supports the + * metadata being transferred as part of an extended data LBA. */ -enum { +enum nvme_id_ns_mc { NVME_NS_MC_EXTENDED = 1 << 0, NVME_NS_MC_SEPARATE = 1 << 1, }; /** - * enum - + * enum nvme_id_ns_dpc - This field indicates the capabilities for the + * end-to-end data protection feature. + * @NVME_NS_DPC_PI_TYPE1: If set, indicates that the namespace supports + * Protection Information Type 1. + * @NVME_NS_DPC_PI_TYPE2: If set, indicates that the namespace supports + * Protection Information Type 2. + * @NVME_NS_DPC_PI_TYPE3: If set, indicates that the namespace supports + * Protection Information Type 3. + * @NVME_NS_DPC_PI_FIRST: If set, indicates that the namespace supports + * protection information transferred as the first eight + * bytes of metadata. + * @NVME_NS_DPC_PI_LAST: If set, indicates that the namespace supports + * protection information transferred as the last eight + * bytes of metadata. */ -enum { +enum nvme_id_ns_dpc { NVME_NS_DPC_PI_TYPE1 = 1 << 0, NVME_NS_DPC_PI_TYPE2 = 1 << 1, NVME_NS_DPC_PI_TYPE3 = 1 << 2, @@ -878,9 +1381,18 @@ enum { }; /** - * enum - + * enum nvme_id_ns_dps - This field indicates the Type settings for the + * end-to-end data protection feature. + * @NVME_NS_DPS_PI_NONE: Protection information is not enabled + * @NVME_NS_DPS_PI_TYPE1: Protection information is enabled, Type 1 + * @NVME_NS_DPS_PI_TYPE2: Protection information is enabled, Type 2 + * @NVME_NS_DPS_PI_TYPE3: Protection information is enabled, Type 3 + * @NVME_NS_DPS_PI_MASK: Mask to get the value of the PI type + * @NVME_NS_DPS_PI_FIRST: If set, indicates that the protection information, if + * enabled, is transferred as the first eight bytes of + * metadata. */ -enum { +enum nvme_id_ns_dps { NVME_NS_DPS_PI_NONE = 0, NVME_NS_DPS_PI_TYPE1 = 1, NVME_NS_DPS_PI_TYPE2 = 2, @@ -890,16 +1402,36 @@ enum { }; /** - * enum - + * enum nvme_id_ns_nmic - This field specifies multi-path I/O and namespace + * sharing capabilities of the namespace. + * @NVME_NS_NMIC_SHARED: If set, then the namespace may be attached to two or + * more controllers in the NVM subsystem concurrently */ -enum { +enum nvme_id_ns_nmic { NVME_NS_NMIC_SHARED = 1 << 0, }; /** - * enum - - */ -enum { + * enum nvme_id_ns_rescap - This field indicates the reservation capabilities + * of the namespace. + * @NVME_NS_RESCAP_PTPL: If set, indicates that the namespace supports the + * Persist Through Power Loss capability. + * @NVME_NS_RESCAP_WE: If set, indicates that the namespace supports the + * Write Exclusive reservation type. + * @NVME_NS_RESCAP_EA: If set, indicates that the namespace supports the + * Exclusive Access reservation type. + * @NVME_NS_RESCAP_WERO: If set, indicates that the namespace supports the + * Write Exclusive - Registrants Only reservation type. + * @NVME_NS_RESCAP_EARO: If set, indicates that the namespace supports the + * Exclusive Access - Registrants Only reservation type. + * @NVME_NS_RESCAP_WEAR: If set, indicates that the namespace supports the + * Write Exclusive - All Registrants reservation type. + * @NVME_NS_RESCAP_EAAR: If set, indicates that the namespace supports the + * Exclusive Access - All Registrants reservation type. + * @NVME_NS_RESCAP_IEK_13: If set, indicates that Ignore Existing Key is used + * as defined in revision 1.3 or later of this specification. + */ +enum nvme_id_ns_rescap { NVME_NS_RESCAP_PTPL = 1 << 0, NVME_NS_RESCAP_WE = 1 << 1, NVME_NS_RESCAP_EA = 1 << 2, @@ -911,17 +1443,38 @@ enum { }; /** - * enum - + * enum nvme_nd_ns_fpi - If a format operation is in progress, this field + * indicates the percentage of the namespace that remains + * to be formatted. + * @NVME_NS_FPI_REMAINING: Mask to get the format percent remaining value + * @NVME_NS_FPI_SUPPORTED: If set, indicates that the namespace supports the + * Format Progress Indicator defined for the field. */ -enum { - NVME_NS_FPI_REMAINING = 127 << 0, +enum nvme_nd_ns_fpi { + NVME_NS_FPI_REMAINING = 0x7f << 0, NVME_NS_FPI_SUPPORTED = 1 << 7, }; /** - * enum - - */ -enum { + * enum nvme_id_ns_dlfeat - This field indicates information about features + * that affect deallocating logical blocks for this + * namespace. + * @NVME_NS_DLFEAT_RB: Mask to get the value of the read behavior + * @NVME_NS_DLFEAT_RB_NR: Read behvaior is not reported + * @NVME_NS_DLFEAT_RB_ALL_0S: A deallocated logical block returns all bytes + * cleared to 0h. + * @NVME_NS_DLFEAT_RB_ALL_FS: A deallocated logical block returns all bytes + * set to FFh. + * @NVME_NS_DLFEAT_WRITE_ZEROES: If set, indicates that the controller supports + * the Deallocate bit in the Write Zeroes command + * for this namespace. + * @NVME_NS_DLFEAT_CRC_GUARD: If set, indicates that the Guard field for + * deallocated logical blocks that contain + * protection information is set to the CRC for + * the value read from the deallocated logical + * block and its metadata + */ +enum nvme_id_ns_dlfeat { NVME_NS_DLFEAT_RB = 7 << 0, NVME_NS_DLFEAT_RB_NR = 0, NVME_NS_DLFEAT_RB_ALL_0S = 1, @@ -931,14 +1484,23 @@ enum { }; /** - * enum - + * enum nvme_id_ns_attr - Specifies attributes of the namespace. + * @NVME_NS_NSATTR_WRITE_PROTECTED: If set, then the namespace is currently + * write protected and all write access to the + * namespace shall fail. */ -enum { +enum nvme_id_ns_attr { NVME_NS_NSATTR_WRITE_PROTECTED = 1 << 0 }; /** * struct nvme_ns_id_desc - + * @nidt: Namespace Identifier Type, see &enum nvme_ns_id_desc_nidt + * @nidl: Namespace Identifier Length contains the length in bytes of the + * &struct nvme_id_ns.nid. + * @nid: Namespace Identifier contains a value that is globally unique and + * assigned to the namespace when the namespace is created. The length + * is defined in &struct nvme_id_ns.nidl. */ struct nvme_ns_id_desc { __u8 nidt; @@ -948,16 +1510,32 @@ struct nvme_ns_id_desc { }; /** - * enum - + * enum nvme_ns_id_desc_nidt - Known namespace identifier types + * @NVME_NIDT_EUI64: IEEE Extended Unique Identifier, the NID field contains a + * copy of the EUI64 field in the struct nvme_id_ns.eui64. + * @NVME_NIDT_NGUID: Namespace Globally Unique Identifier, the NID field + * contains a copy of the NGUID field in struct nvme_id_ns.nguid. + * @NVME_NIDT_UUID: The NID field contains a 128-bit Universally Unique + * Identifier (UUID) as specified in RFC 4122. */ -enum { +enum nvme_ns_id_desc_nidt { NVME_NIDT_EUI64 = 1, NVME_NIDT_NGUID = 2, NVME_NIDT_UUID = 3, }; /** - * struct nvme_nvmset_attr - + * struct nvme_nvmset_attr - NVM Set Attributes Entry + * @id: NVM Set Identifier + * @endurance_group_id: Endurance Group Identifier + * @random_4k_read_typical: Random 4 KiB Read Typical indicates the typical + * time to complete a 4 KiB random read in 100 + * nanosecond units when the NVM Set is in a + * Predictable Latency Mode Deterministic Window and + * there is 1 outstanding command per NVM Set. + * @opt_write_size: + * @total_nvmset_cap: + * @unalloc_nvmset_cap: */ struct nvme_nvmset_attr { __le16 id; @@ -972,6 +1550,8 @@ struct nvme_nvmset_attr { /** * struct nvme_id_nvmset_list - + * @nid; + * @ent:; */ struct nvme_id_nvmset_list { __u8 nid; @@ -981,6 +1561,8 @@ struct nvme_id_nvmset_list { /** * struct nvme_id_ns_granularity_desc - + * @namespace_size_granularity: + * @namespace_capacity_granularity: */ struct nvme_id_ns_granularity_desc { __le64 namespace_size_granularity; @@ -989,6 +1571,9 @@ struct nvme_id_ns_granularity_desc { /** * struct nvme_id_ns_granularity_list - + * @attributes: + * @num_descriptors: + * @entry: */ struct nvme_id_ns_granularity_list { __le32 attributes; @@ -1000,6 +1585,8 @@ struct nvme_id_ns_granularity_list { /** * struct nvme_id_uuid_list_entry - + * @header: + * @uuid: */ struct nvme_id_uuid_list_entry { __u8 header; @@ -1009,6 +1596,10 @@ struct nvme_id_uuid_list_entry { /** * enum - + * @NVME_ID_UUID_HDR_ASSOCIATION_MASK: + * @NVME_ID_UUID_ASSOCIATION_NONE: + * @NVME_ID_UUID_ASSOCIATION_VENDOR: + * @NVME_ID_UUID_ASSOCIATION_SUBSYSTEM_VENDOR: */ enum { NVME_ID_UUID_HDR_ASSOCIATION_MASK = 0x3, @@ -1019,6 +1610,7 @@ enum { /** * struct nvme_id_uuid_list - + * @entry: */ struct nvme_id_uuid_list { __u8 rsvd0[32]; @@ -1027,6 +1619,8 @@ struct nvme_id_uuid_list { /** * struct nvme_ctrl_list - + * @num; + * @identifier: */ struct nvme_ctrl_list { __le16 num; @@ -1035,6 +1629,7 @@ struct nvme_ctrl_list { /** * struct nvme_ns_list - + * @ns: */ struct nvme_ns_list { __le32 ns[NVME_ID_NS_LIST_MAX]; @@ -1042,6 +1637,21 @@ struct nvme_ns_list { /** * struct nvme_primary_ctrl_cap - + * @cntlid: + * @portid: + * @crt: + * @vqfrt: + * @vqrfa: + * @vqrfap: + * @vqprt: + * @vqfrsm: + * @vqgran: + * @vifrt: + * @virfa: + * @virfap: + * @viprt: + * @vifrsm: + * @vigran: */ struct nvme_primary_ctrl_cap { __le16 cntlid; @@ -1066,6 +1676,12 @@ struct nvme_primary_ctrl_cap { /** * struct nvme_secondary_ctrl - + * @scid: + * @pcid: + * @scs: + * @vfn: + * @nvq: + * @nvi: */ struct nvme_secondary_ctrl { __le16 scid; @@ -1080,6 +1696,8 @@ struct nvme_secondary_ctrl { /** * struct nvme_secondary_ctrl_list - + * @num; + * @sc_entry: */ struct nvme_secondary_ctrl_list { __u8 num; @@ -1087,10 +1705,6 @@ struct nvme_secondary_ctrl_list { struct nvme_secondary_ctrl sc_entry[NVME_ID_SECONDARY_CTRL_MAX]; }; -/** - * DOC: NVMe Logs - */ - /** * struct nvme_error_log_page - */ @@ -1112,6 +1726,8 @@ struct nvme_error_log_page { /** * enum - + * @NVME_ERR_PEL_BYTE_MASK: + * @NVME_ERR_PEL_BIT_MASK: */ enum { NVME_ERR_PEL_BYTE_MASK = 0xf, @@ -1120,6 +1736,29 @@ enum { /** * struct nvme_smart_log - + * @critical_warning: + * @temperature: + * @avail_spare: + * @spare_thresh: + * @percent_used: + * @endu_grp_crit_warn_sumry: + * @data_units_read: + * @data_units_written: + * @host_reads: + * @host_writes: + * @ctrl_busy_time: + * @power_cycles: + * @power_on_hours: + * @unsafe_shutdowns: + * @media_errors: + * @num_err_log_entries: + * @warning_temp_time: + * @critical_comp_time: + * @temp_sensor: + * @thm_temp1_trans_count: + * @thm_temp2_trans_count: + * @thm_temp1_total_time: + * @thm_temp2_total_time: */ struct nvme_smart_log { __u8 critical_warning; @@ -1151,6 +1790,12 @@ struct nvme_smart_log { /** * enum - + * @NVME_SMART_CRIT_SPARE: + * @NVME_SMART_CRIT_TEMPERATURE: + * @NVME_SMART_CRIT_DEGRADED: + * @NVME_SMART_CRIT_MEDIA: + * @NVME_SMART_CRIT_VOLATILE_MEMORY: + * @NVME_SMART_CRIT_PMR_RO: */ enum { NVME_SMART_CRIT_SPARE = 1 << 0, @@ -1163,6 +1808,9 @@ enum { /** * enum - + * @NVME_SMART_EGCW_SPARE: + * @NVME_SMART_EGCW_DEGRADED: + * @NVME_SMART_EGCW_RO: */ enum { NVME_SMART_EGCW_SPARE = 1 << 0, @@ -1172,6 +1820,7 @@ enum { /** * struct nvme_frs - + * @frs: */ struct nvme_frs { char frs[8]; @@ -1179,6 +1828,8 @@ struct nvme_frs { /** * struct nvme_firmware_slot - + * @afi: + * @frs: */ struct nvme_firmware_slot { __u8 afi; @@ -1189,6 +1840,8 @@ struct nvme_firmware_slot { /** * struct nvme_cmd_effects_log - + * @acs: + * @iocs: */ struct nvme_cmd_effects_log { __le32 acs[256]; @@ -1198,6 +1851,13 @@ struct nvme_cmd_effects_log { /** * enum - + * @NVME_CMD_EFFECTS_CSUPP: + * @NVME_CMD_EFFECTS_LBCC: + * @NVME_CMD_EFFECTS_NCC: + * @NVME_CMD_EFFECTS_NIC: + * @NVME_CMD_EFFECTS_CCC: + * @NVME_CMD_EFFECTS_CSE_MASK: + * @NVME_CMD_EFFECTS_UUID_SEL: */ enum { NVME_CMD_EFFECTS_CSUPP = 1 << 0, @@ -1211,6 +1871,15 @@ enum { /** * struct nvme_st_result - + * @dsts: + * @seg: + * @vdi: + * @poh: + * @nsid: + * @flba: + * @sct: + * @sc: + * @vs: */ struct nvme_st_result { __u8 dsts; @@ -1227,11 +1896,22 @@ struct nvme_st_result { /** * enum - + * @NVME_ST_RESULT_NO_ERR: + * @NVME_ST_RESULT_ABORTED: + * @NVME_ST_RESULT_CLR: + * @NVME_ST_RESULT_NS_REMOVED: + * @NVME_ST_RESULT_ABORTED_FORMAT: + * @NVME_ST_RESULT_FATAL_ERR: + * @NVME_ST_RESULT_UNKNOWN_SEG_FAIL: + * @NVME_ST_RESULT_KNOWN_SEG_FAIL: + * @NVME_ST_RESULT_ABORTED_UNKNOWN: + * @NVME_ST_RESULT_ABORTED_SANITIZE: + * @NVME_ST_RESULT_NOT_USED: */ enum { NVME_ST_RESULT_NO_ERR = 0x0, NVME_ST_RESULT_ABORTED = 0x1, - NVME_ST_RESULT_CLR = 0x2, + NVME_ST_RESULT_CLR = 0x2, NVME_ST_RESULT_NS_REMOVED = 0x3, NVME_ST_RESULT_ABORTED_FORMAT = 0x4, NVME_ST_RESULT_FATAL_ERR = 0x5, @@ -1244,6 +1924,10 @@ enum { /** * enum - + * @NVME_ST_OPERATION_NONE: + * @NVME_ST_OPERATION_SHORT: + * @NVME_ST_OPERATION_EXTENDED: + * @NVME_ST_OPERATION_VS: */ enum { NVME_ST_OPERATION_NONE = 0x0, @@ -1254,6 +1938,10 @@ enum { /** * enum - + * @NVME_ST_VALID_DIAG_INFO_NSID: + * @NVME_ST_VALID_DIAG_INFO_FLBA: + * @NVME_ST_VALID_DIAG_INFO_SCT: + * @NVME_ST_VALID_DIAG_INFO_SC: */ enum { NVME_ST_VALID_DIAG_INFO_NSID = 1 << 0, @@ -1265,6 +1953,9 @@ enum { /** * struct nvme_self_test_log - + * @current_operation: + * @completion: + * @result: */ struct nvme_self_test_log { __u8 current_operation; @@ -1275,6 +1966,15 @@ struct nvme_self_test_log { /** * struct nvme_telemetry_log - + * @lpi: + * @ieee: + * @dalb1: + * @dalb2: + * @dalb3: + * @ctrlavail: + * @ctrldgn: + * @rsnident: + * @telemetry_dataarea: */ struct nvme_telemetry_log { __u8 lpi; @@ -1292,6 +1992,18 @@ struct nvme_telemetry_log { /** * struct nvme_endurance_group_log - + * @critical_warning: + * @avl_spare: + * @avl_spare_threshold: + * @percent_used: + * @endurance_estimate: + * @data_units_read: + * @data_units_written: + * @media_units_written: + * @host_read_cmds: + * @host_write_cmds: + * @media_data_integrity_err: + * @num_err_info_log_entries: */ struct nvme_endurance_group_log { __u8 critical_warning; @@ -1313,6 +2025,9 @@ struct nvme_endurance_group_log { /** * enum - + * @NVME_EG_CRITICAL_WARNING_SPARE: + * @NVME_EG_CRITICAL_WARNING_DEGRADED: + * @NVME_EG_CRITICAL_WARNING_READ_ONLY: */ enum nvme_eg_critical_warning_flags { NVME_EG_CRITICAL_WARNING_SPARE = 1 << 0, @@ -1322,6 +2037,8 @@ enum nvme_eg_critical_warning_flags { /** * struct nvme_aggregate_endurance_group_event - + * @num_entries: + * @entries: */ struct nvme_aggregate_endurance_group_event { __le64 num_entries; @@ -1330,6 +2047,16 @@ struct nvme_aggregate_endurance_group_event { /** * struct nvme_nvmset_predictable_lat_log - + * @status: + * @event_type: + * @dtwin_rt: + * @dtwin_wt: + * @dtwin_tmax: + * @dtwin_tmin_hi: + * @dtwin_tmin_lo: + * @dtwin_re: + * @dtwin_we: + * @dtwin_te: */ struct nvme_nvmset_predictable_lat_log { __u8 status; @@ -1350,6 +2077,9 @@ struct nvme_nvmset_predictable_lat_log { /** * enum - + * @NVME_NVMSET_PL_STATUS_DISABLED: + * @NVME_NVMSET_PL_STATUS_DTWIN: + * @NVME_NVMSET_PL_STATUS_NDWIN: */ enum { NVME_NVMSET_PL_STATUS_DISABLED = 0, @@ -1359,6 +2089,11 @@ enum { /** * enum - + * @NVME_NVMSET_PL_EVENT_DTWIN_READ_WARN: + * @NVME_NVMSET_PL_EVENT_DTWIN_WRITE_WARN: + * @NVME_NVMSET_PL_EVENT_DTWIN_TIME_WARN: + * @NVME_NVMSET_PL_EVENT_DTWIN_EXCEEDED: + * @NVME_NVMSET_PL_EVENT_DTWIN_EXCURSION: */ enum { NVME_NVMSET_PL_EVENT_DTWIN_READ_WARN = 1 << 0, @@ -1370,6 +2105,8 @@ enum { /** * struct nvme_aggregate_predictable_lat_event - + * @num_entries: + * @entries: */ struct nvme_aggregate_predictable_lat_event { __le64 num_entries; @@ -1378,6 +2115,11 @@ struct nvme_aggregate_predictable_lat_event { /** * struct nvme_ana_group_desc - + * @grpid: + * @nnsids: + * @chgcnt: + * @state: + * @nsids: */ struct nvme_ana_group_desc { __le32 grpid; @@ -1390,6 +2132,11 @@ struct nvme_ana_group_desc { /** * enum - + * @NVME_ANA_STATE_OPTIMIZED: + * @NVME_ANA_STATE_NONOPTIMIZED: + * @NVME_ANA_STATE_INACCESSIBLE: + * @NVME_ANA_STATE_PERSISTENT_LOSS: + * @NVME_ANA_STATE_CHANGE: */ enum { NVME_ANA_STATE_OPTIMIZED = 0x1, @@ -1401,6 +2148,9 @@ enum { /** * struct nvme_ana_log - + * @chgcnt: + * @ngrps: + * @descs: */ struct nvme_ana_log { __le64 chgcnt; @@ -1411,6 +2161,19 @@ struct nvme_ana_log { /** * struct nvme_persistent_event_log - + * @lid: + * @ttl: + * @rv: + * @lht: + * @ts: + * @poh: + * @pcc: + * @vid: + * @ssvid: + * @sn: + * @mn: + * @subnqn: + * @seb: */ struct nvme_persistent_event_log { __u8 lid; @@ -1433,6 +2196,8 @@ struct nvme_persistent_event_log { /** * struct nvme_lba_rd - + * @rslba: + * @rnlb: */ struct nvme_lba_rd { __le64 rslba; @@ -1442,6 +2207,10 @@ struct nvme_lba_rd { /** * struct nvme_lbas_ns_element - + * @neid: + * @nrld: + * @ratype: + * @lba_rd: */ struct nvme_lbas_ns_element { __le32 neid; @@ -1463,6 +2232,11 @@ enum nvme_lba_status_atype { /** * struct nvme_lba_status_log - + * @lslplen: + * @nlslne: + * @estulb: + * @lsgc: + * @elements: */ struct nvme_lba_status_log { __le32 lslplen; @@ -1475,6 +2249,8 @@ struct nvme_lba_status_log { /** * struct nvme_eg_event_aggregate_log - + * @nr_entries: + * @egids: */ struct nvme_eg_event_aggregate_log { __le64 nr_entries; @@ -1483,6 +2259,10 @@ struct nvme_eg_event_aggregate_log { /** * struct nvme_resv_notification_log - + * @lpc: + * @rnlpt: + * @nalp: + * @nsid: */ struct nvme_resv_notification_log { __le64 lpc; @@ -1495,6 +2275,10 @@ struct nvme_resv_notification_log { /** * enum - + * @NVME_RESV_NOTIFY_RNLPT_EMPTY: + * @NVME_RESV_NOTIFY_RNLPT_REGISTRATION_PREEMPTED: + * @NVME_RESV_NOTIFY_RNLPT_RESERVATION_RELEASED: + * @NVME_RESV_NOTIFY_RNLPT_RESERVATION_PREEMPTED: */ enum { NVME_RESV_NOTIFY_RNLPT_EMPTY = 0, @@ -1505,6 +2289,15 @@ enum { /** * struct nvme_sanitize_log_page - + * @sprog: + * @sstat: + * @scdw10: + * @eto: + * @etbe: + * @etce: + * @etond: + * @etbend: + * @etcend: */ struct nvme_sanitize_log_page { __le16 sprog; @@ -1519,12 +2312,13 @@ struct nvme_sanitize_log_page { __u8 rsvd32[480]; }; -/** - * DOC: NVMe Directives - */ - /** * enum - + * @NVME_SANITIZE_SSTAT_NEVER_SANITIZED: + * @NVME_SANITIZE_SSTAT_COMPLETE_SUCCESS: + * @NVME_SANITIZE_SSTAT_IN_PROGESS: + * @NVME_SANITIZE_SSTAT_COMPLETED_FAILED: + * @NVME_SANITIZE_SSTAT_ND_COMPLETE_SUCCESS: */ enum { NVME_SANITIZE_SSTAT_NEVER_SANITIZED = 0, @@ -1536,17 +2330,23 @@ enum { /** * struct nvme_lba_status_desc - + * @dslba: + * @nlb: + * @status: */ struct nvme_lba_status_desc { - __le64 dslba; - __le32 nlb; - __u8 rsvd12; - __u8 status; - __u8 rsvd14[2]; + __le64 dslba; + __le32 nlb; + __u8 rsvd12; + __u8 status; + __u8 rsvd14[2]; }; /** * struct nvme_lba_status - + * @nlsd: + * @cmpc: + * @descs: */ struct nvme_lba_status { __le32 nlsd; @@ -1555,345 +2355,122 @@ struct nvme_lba_status { struct nvme_lba_status_desc descs[]; }; - -/** - * DOC: NVMe Management Interface - */ - /** - * struct nvme_mi_read_nvm_ss_info - + * struct nvme_feat_auto_pst - + * @apst_entry: */ -struct nvme_mi_read_nvm_ss_info { - __u8 nump; - __u8 mjr; - __u8 mnr; - __u8 rsvd3[29]; +struct nvme_feat_auto_pst { + __le64 apst_entry[32]; }; /** - * struct nvme_mi_port_pcie - + * struct nvme_timestamp - + * timestamp: + * @attr: */ -struct nvme_mi_port_pcie { - __u8 mps; - __u8 sls; - __u8 cls; - __u8 mlw; - __u8 nlw; - __u8 pn; - __u8 rsvd14[18]; +struct nvme_timestamp { + __u8 timestamp[6]; + __u8 attr; + __u8 rsvd; }; /** - * struct nvme_mi_port_smb - + * struct nvme_lba_range_type_entry - + * @type: + * @attributes: + * @slba: + * @nlb: + * @guid: */ -struct nvme_mi_port_smb { - __u8 vpd_addr; - __u8 mvpd_freq; - __u8 mme_addr; - __u8 mme_freq; - __u8 nvmebm; - __u8 rsvd13[19]; +struct nvme_lba_range_type_entry { + __u8 type; + __u8 attributes; + __u8 rsvd2[14]; + __u64 slba; + __u64 nlb; + __u8 guid[16]; + __u8 rsvd48[16]; }; /** - * struct nvme_mi_read_port_info - + * enum - + * @NVME_LBART_TYPE_GP: + * @NVME_LBART_TYPE_FS: + * @NVME_LBART_TYPE_RAID: + * @NVME_LBART_TYPE_CACHE: + * @NVME_LBART_TYPE_SWAP: + * @NVME_LBART_ATTRIB_TEMP: + * @NVME_LBART_ATTRIB_HIDE: */ -struct nvme_mi_read_port_info { - __u8 portt; - __u8 rsvd1; - __le16 mmctptus; - __le32 meb; - union { - struct nvme_mi_port_pcie pcie; - struct nvme_mi_port_smb smb; - }; +enum { + NVME_LBART_TYPE_GP = 0, + NVME_LBART_TYPE_FS = 1, + NVME_LBART_TYPE_RAID = 2, + NVME_LBART_TYPE_CACHE = 3, + NVME_LBART_TYPE_SWAP = 4, + NVME_LBART_ATTRIB_TEMP = 1 << 0, + NVME_LBART_ATTRIB_HIDE = 1 << 1, }; /** - * struct nvme_mi_read_ctrl_info - + * struct nvme_lba_range_type - + * @entry: */ -struct nvme_mi_read_ctrl_info { - __u8 portid; - __u8 rsvd1[4]; - __u8 prii; - __le16 pri; - __le16 vid; - __le16 did; - __le16 ssvid; - __le16 ssid; - __u8 rsvd16[16]; +struct nvme_lba_range_type { + struct nvme_lba_range_type_entry entry[NVME_FEAT_LBA_RANGE_MAX]; }; /** - * struct nvme_mi_osc - + * struct nvme_plm_config - + * @ee; + * @dtwinrt; + * @dtwinwt; + * @dtwintt; */ -struct nvme_mi_osc { - __u8 type; - __u8 opc; +struct nvme_plm_config { + __le16 ee; + __u8 rsvd2[30]; + __le64 dtwinrt; + __le64 dtwinwt; + __le64 dtwintt; + __u8 rsvd56[456]; }; /** - * struct nvme_mi_read_sc_list - + * struct nvme_feat_host_behavior - + * @acre: */ -struct nvme_mi_read_sc_list { - __le16 numcmd; - struct nvme_mi_osc cmds[]; +struct nvme_feat_host_behavior { + __u8 acre; + __u8 resv1[511]; }; /** - * struct nvme_mi_nvm_ss_health_status - + * enum - + * @NVME_ENABLE_ACRE: */ -struct nvme_mi_nvm_ss_health_status { - __u8 nss; - __u8 sw; - __u8 ctemp; - __u8 pdlu; - __le16 ccs; - __u8 rsvd8[2]; +enum { + NVME_ENABLE_ACRE = 1 << 0, }; /** - * enum - + * struct nvme_dsm_range - + * @cattr: + * @nlb: + * @slba: */ -enum { - NVME_MI_CCS_RDY = 1 << 0, - NVME_MI_CSS_CFS = 1 << 1, - NVME_MI_CSS_SHST = 1 << 2, - NVME_MI_CSS_NSSRO = 1 << 4, - NVME_MI_CSS_CECO = 1 << 5, - NVME_MI_CSS_NAC = 1 << 6, - NVME_MI_CSS_FA = 1 << 7, - NVME_MI_CSS_CSTS = 1 << 8, - NVME_MI_CSS_CTEMP = 1 << 9, - NVME_MI_CSS_PDLU = 1 << 10, - NVME_MI_CSS_SPARE = 1 << 11, - NVME_MI_CSS_CCWARN = 1 << 12, +struct nvme_dsm_range { + __le32 cattr; + __le32 nlb; + __le64 slba; }; /** - * struct nvme_mi_ctrl_heal_status - - */ -struct nvme_mi_ctrl_heal_status { - __le16 ctlid; - __le16 csts; - __le16 ctemp; - __u8 pdlu; - __u8 spare; - __u8 cwarn; - __u8 rsvd9[7]; -}; - -/** - * enum - - */ -enum { - NVME_MI_CSTS_RDY = 1 << 0, - NVME_MI_CSTS_CFS = 1 << 1, - NVME_MI_CSTS_SHST = 1 << 2, - NVME_MI_CSTS_NSSRO = 1 << 4, - NVME_MI_CSTS_CECO = 1 << 5, - NVME_MI_CSTS_NAC = 1 << 6, - NVME_MI_CSTS_FA = 1 << 7, - NVME_MI_CWARN_ST = 1 << 0, - NVME_MI_CWARN_TAUT = 1 << 1, - NVME_MI_CWARN_RD = 1 << 2, - NVME_MI_CWARN_RO = 1 << 3, - NVME_MI_CWARN_VMBF = 1 << 4, -}; - -/** - * struct nvme_mi_vpd_mra - - */ -struct nvme_mi_vpd_mra { - __u8 nmravn; - __u8 ff; - __u8 rsvd7[6]; - __u8 i18vpwr; - __u8 m18vpwr; - __u8 i33vpwr; - __u8 m33vpwr; - __u8 rsvd17; - __u8 m33vapsr; - __u8 i5vapsr; - __u8 m5vapsr; - __u8 i12vapsr; - __u8 m12vapsr; - __u8 mtl; - __u8 tnvmcap[16]; - __u8 rsvd37[27]; -}; - -/** - * struct nvme_mi_vpd_ppmra - - */ -struct nvme_mi_vpd_ppmra { - __u8 nppmravn; - __u8 pn; - __u8 ppi; - __u8 ls; - __u8 mlw; - __u8 mctp; - __u8 refccap; - __u8 pi; - __u8 rsvd13[3]; -}; - -/** - * struct nvme_mi_vpd_telem - - */ -struct nvme_mi_vpd_telem { - __u8 type; - __u8 rev; - __u8 len; - __u8 data[0]; -}; - -/** - * enum - - */ -enum { - NVME_MI_ELEM_EED = 1, - NVME_MI_ELEM_USCE = 2, - NVME_MI_ELEM_ECED = 3, - NVME_MI_ELEM_LED = 4, - NVME_MI_ELEM_SMBMED = 5, - NVME_MI_ELEM_PCIESED = 6, - NVME_MI_ELEM_NVMED = 7, -}; - -/** - * struct nvme_mi_vpd_tra - - */ -struct nvme_mi_vpd_tra { - __u8 vn; - __u8 rsvd6; - __u8 ec; - struct nvme_mi_vpd_telem elems[0]; -}; - -/** - * struct nvme_mi_vpd_mr_common - - */ -struct nvme_mi_vpd_mr_common { - __u8 type; - __u8 rf; - __u8 rlen; - __u8 rchksum; - __u8 hchksum; - - union { - struct nvme_mi_vpd_mra nmra; - struct nvme_mi_vpd_ppmra ppmra; - struct nvme_mi_vpd_tra tmra; - }; -}; - -/** - * struct nvme_mi_vpd_hdr - - */ -struct nvme_mi_vpd_hdr { - __u8 ipmiver; - __u8 iuaoff; - __u8 ciaoff; - __u8 biaoff; - __u8 piaoff; - __u8 mrioff; - __u8 rsvd6; - __u8 chchk; - __u8 vpd[]; -}; - -/** - * DOC: NVMe Features - */ - -/** - * struct nvme_feat_auto_pst - - */ -struct nvme_feat_auto_pst { - __le64 apst_entry[32]; -}; - -/** - * struct nvme_timestamp - - */ -struct nvme_timestamp { - __u8 timestamp[6]; - __u8 attr; - __u8 rsvd; -}; - -/** - * struct nvme_lba_range_type_entry - - */ -struct nvme_lba_range_type_entry { - __u8 type; - __u8 attributes; - __u8 rsvd2[14]; - __u64 slba; - __u64 nlb; - __u8 guid[16]; - __u8 rsvd48[16]; -}; - -/** - * enum - - */ -enum { - NVME_LBART_TYPE_GP = 0, - NVME_LBART_TYPE_FS = 1, - NVME_LBART_TYPE_RAID = 2, - NVME_LBART_TYPE_CACHE = 3, - NVME_LBART_TYPE_SWAP = 4, - NVME_LBART_ATTRIB_TEMP = 1 << 0, - NVME_LBART_ATTRIB_HIDE = 1 << 1, -}; - -/** - * struct nvme_lba_range_type - - */ -struct nvme_lba_range_type { - struct nvme_lba_range_type_entry entry[NVME_FEAT_LBA_RANGE_MAX]; -}; - -/** - * struct nvme_plm_config - - */ -struct nvme_plm_config { - __le16 ee; - __u8 rsvd2[30]; - __le64 dtwinrt; - __le64 dtwinwt; - __le64 dtwintt; - __u8 rsvd56[456]; -}; - -/** - * struct nvme_feat_host_behavior - - */ -struct nvme_feat_host_behavior { - __u8 acre; - __u8 resv1[511]; -}; - -/** - * enum - - */ -enum { - NVME_ENABLE_ACRE = 1 << 0, -}; - -/** - * struct nvme_dsm_range - - */ -struct nvme_dsm_range { - __le32 cattr; - __le32 nlb; - __le64 slba; -}; - -/** - * struct nvme_registered_ctrl - + * struct nvme_registered_ctrl - + * @cntlid: + * @rcsts: + * @hostid: + * @rkey: */ struct nvme_registered_ctrl { __le16 cntlid; @@ -1905,6 +2482,10 @@ struct nvme_registered_ctrl { /** * struct nvme_registered_ctrl_ext - + * @cntlid: + * @rcsts: + * @rkey: + * @hostid: */ struct nvme_registered_ctrl_ext { __le16 cntlid; @@ -1916,7 +2497,13 @@ struct nvme_registered_ctrl_ext { }; /** - * struct nvme_reservation_status - + * struct nvme_reservation_status -{ + * @gen: + * @rtype: + * @regctl: + * @ptpls: + * @regctl_eds: + * @regctl_ds: */ struct nvme_reservation_status { __le32 gen; @@ -2194,9 +2781,23 @@ enum nvme_subsys_type { #define NVMF_TSAS_SIZE 256 /** - * struct nvmf_disc_log_entry - - * - * Discovery log page entry + * struct nvmf_disc_log_entry - Discovery log page entry + * @trtype: + * @adrfam: + * @subtype: + * @treq: + * @portid: + * @cntlid: + * @asqsz: + * @trsvcid: + * @subnqn: + * @traddr: + * @common: + * @qptype: + * @prtype: + * @cms: + * @pkey: + * @sectype: */ struct nvmf_disc_log_entry { __u8 trtype; @@ -2228,14 +2829,12 @@ struct nvmf_disc_log_entry { }; /** - * enum - + * enum - Transport Type codes for Discovery Log Page entry TRTYPE field * @NVMF_TRTYPE_UNSPECIFIED: Not indicated * @NVMF_TRTYPE_RDMA: RDMA * @NVMF_TRTYPE_FC: Fibre Channel * @NVMF_TRTYPE_TCP: TCP * @NVMF_TRTYPE_LOOP: Reserved for host usage - * - * Transport Type codes for Discovery Log Page entry TRTYPE field */ enum { NVMF_TRTYPE_UNSPECIFIED = 0, @@ -2247,14 +2846,12 @@ enum { }; /** - * enum - + * enum - Address Family codes for Discovery Log Page entry ADRFAM field * @NVMF_ADDR_FAMILY_PCI: PCIe * @NVMF_ADDR_FAMILY_IP4: IPv4 * @NVMF_ADDR_FAMILY_IP6: IPv6 * @NVMF_ADDR_FAMILY_IB: InfiniBand * @NVMF_ADDR_FAMILY_FC: Fibre Channel - * - * Address Family codes for Discovery Log Page entry ADRFAM field */ enum { NVMF_ADDR_FAMILY_PCI = 0, @@ -2265,13 +2862,11 @@ enum { }; /** - * enum - + * enum - Transport Requirements codes for Discovery Log Page entry TREQ field * @NVMF_TREQ_NOT_SPECIFIED: Not specified * @NVMF_TREQ_REQUIRED: Required * @NVMF_TREQ_NOT_REQUIRED: Not Required * @NVMF_TREQ_DISABLE_SQFLOW: SQ flow control disable supported - * - * Transport Requirements codes for Discovery Log Page entry TREQ field */ enum { NVMF_TREQ_NOT_SPECIFIED = 0, @@ -2281,12 +2876,10 @@ enum { }; /** - * enum - + * enum - RDMA QP Service Type codes for Discovery Log Page entry TSAS + * RDMA_QPTYPE field * @NVMF_RDMA_QPTYPE_CONNECTED: Reliable Connected * @NVMF_RDMA_QPTYPE_DATAGRAM: Reliable Datagram - * - * RDMA QP Service Type codes for Discovery Log Page entry TSAS - * RDMA_QPTYPE field */ enum { NVMF_RDMA_QPTYPE_CONNECTED = 1, @@ -2294,15 +2887,13 @@ enum { }; /** - * enum - - * @NVMF_RDMA_PRTYPE_NOT_SPECIFIED: No Provider Specified - * @NVMF_RDMA_PRTYPE_IB: InfiniBand - * @NVMF_RDMA_PRTYPE_ROCE: InfiniBand RoCE - * @NVMF_RDMA_PRTYPE_ROCEV2: InfiniBand RoCEV2 - * @NVMF_RDMA_PRTYPE_IWARP: iWARP - * - * RDMA Provider Type codes for Discovery Log Page entry TSAS - * RDMA_PRTYPE field + * enum - RDMA Provider Type codes for Discovery Log Page entry TSAS + * RDMA_PRTYPE field + * @NVMF_RDMA_PRTYPE_NOT_SPECIFIED: No Provider Specified + * @NVMF_RDMA_PRTYPE_IB: InfiniBand + * @NVMF_RDMA_PRTYPE_ROCE: InfiniBand RoCE + * @NVMF_RDMA_PRTYPE_ROCEV2: InfiniBand RoCEV2 + * @NVMF_RDMA_PRTYPE_IWARP: iWARP */ enum { NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, @@ -2313,11 +2904,10 @@ enum { }; /** - * enum - - * @NVMF_RDMA_CMS_RDMA_CM: Sockets based endpoint addressing + * enum - RDMA Connection Management Service Type codes for Discovery Log Page + * entry TSAS RDMA_CMS field + * @NVMF_RDMA_CMS_RDMA_CM: Sockets based endpoint addressing * - * RDMA Connection Management Service Type codes for Discovery Log Page - * entry TSAS RDMA_CMS field */ enum { NVMF_RDMA_CMS_RDMA_CM = 1, @@ -2325,8 +2915,8 @@ enum { /** * enum - - * @NVMF_TCP_SECTYPE_NONE: No Security - * @NVMF_TCP_SECTYPE_TLS: Transport Layer Security + * @NVMF_TCP_SECTYPE_NONE: No Security + * @NVMF_TCP_SECTYPE_TLS: Transport Layer Security */ enum { NVMF_TCP_SECTYPE_NONE = 0, @@ -2335,6 +2925,10 @@ enum { /** * struct nvmf_discovery_log - + * @genctr: + * @numrec: + * @recfmt: + * @entries: */ struct nvmf_discovery_log { __le64 genctr; @@ -2346,6 +2940,10 @@ struct nvmf_discovery_log { /** * struct nvmf_connect_data - + * @hostid: + * @cntlid: + * @subsysnqn + * @hostnqn */ struct nvmf_connect_data { __u8 hostid[16]; @@ -2356,6 +2954,365 @@ struct nvmf_connect_data { char resv5[256]; }; +/** + * struct nvme_mi_read_nvm_ss_info - + * @nump: + * @mjr: + * @mnr: + */ +struct nvme_mi_read_nvm_ss_info { + __u8 nump; + __u8 mjr; + __u8 mnr; + __u8 rsvd3[29]; +}; + +/** + * struct nvme_mi_port_pcie - + * @mps: + * @sls: + * @cls: + * @mlw: + * @nlw: + * @pn: + */ +struct nvme_mi_port_pcie { + __u8 mps; + __u8 sls; + __u8 cls; + __u8 mlw; + __u8 nlw; + __u8 pn; + __u8 rsvd14[18]; +}; + +/** + * struct nvme_mi_port_smb - + * @vpd_addr: + * @mvpd_freq: + * @mme_addr: + * @mme_freq: + * @nvmebm: + */ +struct nvme_mi_port_smb { + __u8 vpd_addr; + __u8 mvpd_freq; + __u8 mme_addr; + __u8 mme_freq; + __u8 nvmebm; + __u8 rsvd13[19]; +}; + +/** + * struct nvme_mi_read_port_info - + * @portt: + * @mmctptus; + * @meb: + * @pcie: + * @smb: + */ +struct nvme_mi_read_port_info { + __u8 portt; + __u8 rsvd1; + __le16 mmctptus; + __le32 meb; + union { + struct nvme_mi_port_pcie pcie; + struct nvme_mi_port_smb smb; + }; +}; + +/** + * struct nvme_mi_read_ctrl_info - + * @portid; + * @prii; + * @pri; + * @vid; + * @did; + * @ssvid; + * @ssid; + */ +struct nvme_mi_read_ctrl_info { + __u8 portid; + __u8 rsvd1[4]; + __u8 prii; + __le16 pri; + __le16 vid; + __le16 did; + __le16 ssvid; + __le16 ssid; + __u8 rsvd16[16]; +}; + +/** + * struct nvme_mi_osc - + * @type; + * @opc; + */ +struct nvme_mi_osc { + __u8 type; + __u8 opc; +}; + +/** + * struct nvme_mi_read_sc_list - + * @numcmd: + * @cmds: + */ +struct nvme_mi_read_sc_list { + __le16 numcmd; + struct nvme_mi_osc cmds[]; +}; + +/** + * struct nvme_mi_nvm_ss_health_status - + * @nss: + * @sw: + * @ctemp: + * @pdlu: + * @ccs: + */ +struct nvme_mi_nvm_ss_health_status { + __u8 nss; + __u8 sw; + __u8 ctemp; + __u8 pdlu; + __le16 ccs; + __u8 rsvd8[2]; +}; + +/** + * enum - + * @NVME_MI_CCS_RDY: + * @NVME_MI_CSS_CFS: + * @NVME_MI_CSS_SHST: + * @NVME_MI_CSS_NSSRO: + * @NVME_MI_CSS_CECO: + * @NVME_MI_CSS_NAC: + * @NVME_MI_CSS_FA: + * @NVME_MI_CSS_CSTS: + * @NVME_MI_CSS_CTEMP: + * @NVME_MI_CSS_PDLU: + * @NVME_MI_CSS_SPARE: + * @NVME_MI_CSS_CCWARN: + */ +enum { + NVME_MI_CCS_RDY = 1 << 0, + NVME_MI_CSS_CFS = 1 << 1, + NVME_MI_CSS_SHST = 1 << 2, + NVME_MI_CSS_NSSRO = 1 << 4, + NVME_MI_CSS_CECO = 1 << 5, + NVME_MI_CSS_NAC = 1 << 6, + NVME_MI_CSS_FA = 1 << 7, + NVME_MI_CSS_CSTS = 1 << 8, + NVME_MI_CSS_CTEMP = 1 << 9, + NVME_MI_CSS_PDLU = 1 << 10, + NVME_MI_CSS_SPARE = 1 << 11, + NVME_MI_CSS_CCWARN = 1 << 12, +}; + +/** + * struct nvme_mi_ctrl_heal_status - + * @ctlid: + * @csts: + * @ctemp: + * @pdlu: + * @spare: + * @cwarn: + */ +struct nvme_mi_ctrl_heal_status { + __le16 ctlid; + __le16 csts; + __le16 ctemp; + __u8 pdlu; + __u8 spare; + __u8 cwarn; + __u8 rsvd9[7]; +}; + +/** + * enum - + * @NVME_MI_CSTS_RDY: + * @NVME_MI_CSTS_CFS: + * @NVME_MI_CSTS_SHST: + * @NVME_MI_CSTS_NSSRO: + * @NVME_MI_CSTS_CECO: + * @NVME_MI_CSTS_NAC: + * @NVME_MI_CSTS_FA: + * @NVME_MI_CWARN_ST: + * @NVME_MI_CWARN_TAUT: + * @NVME_MI_CWARN_RD: + * @NVME_MI_CWARN_RO: + * @NVME_MI_CWARN_VMBF: + */ +enum { + NVME_MI_CSTS_RDY = 1 << 0, + NVME_MI_CSTS_CFS = 1 << 1, + NVME_MI_CSTS_SHST = 1 << 2, + NVME_MI_CSTS_NSSRO = 1 << 4, + NVME_MI_CSTS_CECO = 1 << 5, + NVME_MI_CSTS_NAC = 1 << 6, + NVME_MI_CSTS_FA = 1 << 7, + NVME_MI_CWARN_ST = 1 << 0, + NVME_MI_CWARN_TAUT = 1 << 1, + NVME_MI_CWARN_RD = 1 << 2, + NVME_MI_CWARN_RO = 1 << 3, + NVME_MI_CWARN_VMBF = 1 << 4, +}; + +/** + * struct nvme_mi_vpd_mra - + * @nmravn; + * @ff; + * @i18vpwr; + * @m18vpwr; + * @i33vpwr; + * @m33vpwr; + * @m33vapsr; + * @i5vapsr; + * @m5vapsr; + * @i12vapsr; + * @m12vapsr; + * @mtl; + * @tnvmcap[16]; + */ +struct nvme_mi_vpd_mra { + __u8 nmravn; + __u8 ff; + __u8 rsvd7[6]; + __u8 i18vpwr; + __u8 m18vpwr; + __u8 i33vpwr; + __u8 m33vpwr; + __u8 rsvd17; + __u8 m33vapsr; + __u8 i5vapsr; + __u8 m5vapsr; + __u8 i12vapsr; + __u8 m12vapsr; + __u8 mtl; + __u8 tnvmcap[16]; + __u8 rsvd37[27]; +}; + +/** + * struct nvme_mi_vpd_ppmra - + * @nppmravn: + * @pn: + * @ppi: + * @ls: + * @mlw: + * @mctp: + * @refccap: + * @pi: + */ +struct nvme_mi_vpd_ppmra { + __u8 nppmravn; + __u8 pn; + __u8 ppi; + __u8 ls; + __u8 mlw; + __u8 mctp; + __u8 refccap; + __u8 pi; + __u8 rsvd13[3]; +}; + +/** + * struct nvme_mi_vpd_telem - + * @type: + * @rev: + * @len: + * @data: + */ +struct nvme_mi_vpd_telem { + __u8 type; + __u8 rev; + __u8 len; + __u8 data[0]; +}; + +/** + * enum - + * @NVME_MI_ELEM_EED: + * @NVME_MI_ELEM_USCE: + * @NVME_MI_ELEM_ECED: + * @NVME_MI_ELEM_LED: + * @NVME_MI_ELEM_SMBMED: + * @NVME_MI_ELEM_PCIESED: + * @NVME_MI_ELEM_NVMED: + */ +enum { + NVME_MI_ELEM_EED = 1, + NVME_MI_ELEM_USCE = 2, + NVME_MI_ELEM_ECED = 3, + NVME_MI_ELEM_LED = 4, + NVME_MI_ELEM_SMBMED = 5, + NVME_MI_ELEM_PCIESED = 6, + NVME_MI_ELEM_NVMED = 7, +}; + +/** + * struct nvme_mi_vpd_tra - + * @vn: + * @ec: + * @elems: + */ +struct nvme_mi_vpd_tra { + __u8 vn; + __u8 rsvd6; + __u8 ec; + struct nvme_mi_vpd_telem elems[0]; +}; + +/** + * struct nvme_mi_vpd_mr_common - + * @type; + * @rf; + * @rlen; + * @rchksum; + * @hchksum; +nmra; + * @ppmra; + * @tmra; + */ +struct nvme_mi_vpd_mr_common { + __u8 type; + __u8 rf; + __u8 rlen; + __u8 rchksum; + __u8 hchksum; + + union { + struct nvme_mi_vpd_mra nmra; + struct nvme_mi_vpd_ppmra ppmra; + struct nvme_mi_vpd_tra tmra; + }; +}; + +/** + * struct nvme_mi_vpd_hdr - + * @ipmiver: + * @iuaoff: + * @ciaoff: + * @biaoff: + * @piaoff: + * @mrioff: + * @chchk: + * @vpd: + */ +struct nvme_mi_vpd_hdr { + __u8 ipmiver; + __u8 iuaoff; + __u8 ciaoff; + __u8 biaoff; + __u8 piaoff; + __u8 mrioff; + __u8 rsvd6; + __u8 chchk; + __u8 vpd[]; +}; + /** * enum - */