From: wdenk Date: Tue, 2 Apr 2002 08:45:48 +0000 (+0000) Subject: * I2C patch (Jerry Van Baren, 2 Apr 2002) X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=0f1dff8c81328f46fa6fbfabd61fd0901c9f4ddf;p=users%2Frw%2Fppcboot.git * I2C patch (Jerry Van Baren, 2 Apr 2002) * Fix I2C on 4xx (again; Erik Theisen, 2 Apr 2002) * Add remaining OCM init fixes (Andrew May, 1 Apr 2002) --- diff --git a/CHANGELOG b/CHANGELOG index 0fc78aa..99ddc38 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,12 @@ Modifications for 1.1.6: ====================================================================== +* I2C patch (Jerry Van Baren, 2 Apr 2002) + +* Fix I2C on 4xx (again; Erik Theisen, 2 Apr 2002) + +* Add remaining OCM init fixes (Andrew May, 1 Apr 2002) + * 405GP I2C ehancements Patch by Andrew May, 29 Mar 2002 diff --git a/README b/README index 6850b49..98513db 100644 --- a/README +++ b/README @@ -610,18 +610,69 @@ The following options need to be configured: on those systems that support this (optional) feature, like the TQM8xxL modules. -- I2C Support: CONFIG_I2C +- I2C Support: CONFIG_HARD_I2C | CONFIG_SOFT_I2C - Enables I2C driver + Enables I2C serial bus commands. If this is selected, + either CONFIG_HARD_I2C or CONFIG_SOFT_I2C must be defined + to include the appropriate I2C driver. - CONFIG_I2C_X + See also: common/cmd_i2c.c for a description of the + command line interface. - Enables extended (16-bit) I2C addressing. + CONFIG_HARD_I2C + + Selects the CPM hardware driver for I2C. + CONFIG_SOFT_I2C Use software (aka bit-banging) driver instead of CPM - or similar hardware support for I2C + or similar hardware support for I2C. This is configured + via the following defines. + + I2C_INIT + + (Optional). Any commands necessary to enable I2C + controller or configure ports. + + I2C_PORT + + (Only for MPC8260 CPU). The I/O port to use (the code + assumes both bits are on the same port). Valid values + are 0..3 for ports A..D. + + I2C_ACTIVE + + The code necessary to make the I2C data line active + (driven). If the data line is open collector, this + define can be null. + + I2C_TRISTATE + + The code necessary to make the I2C data line tri-stated + (inactive). If the data line is open collector, this + define can be null. + + I2C_READ + + Code that returns TRUE if the I2C data line is high, + FALSE if it is low. + + I2C_SDA(bit) + + If is TRUE, sets the I2C data line high. If it + is FALSE, it clears it (low). + + I2C_SCL(bit) + + If is TRUE, sets the I2C clock line high. If it + is FALSE, it clears it (low). + + I2C_DELAY + + This delay is invoked four times per clock cycle so this + controls the rate of data transfer. The data rate thus + is 1 / (I2C_DELAY * 4). - SPI Support: CONFIG_SPI diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index d856760..eda00fc 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -22,9 +22,63 @@ */ /* - * I2C Functions just like the standard memory functions + * I2C Functions similar to the standard memory functions. * - * Adapted from cmd_mem.c, Wolfgang Denk (wd@denx.de). + * There are several parameters in many of the commands that bear further + * explanations: + * + * Two of the commands (imm and imw) take a byte/word/long modifier + * (e.g. imm.w specifies the word-length modifier). This was done to + * allow manipulating word-length registers. It was not done on any other + * commands because it was not deemed useful. + * + * {i2c_chip} is the I2C chip address (the first byte sent on the bus). + * Each I2C chip on the bus has a unique address. On the I2C data bus, + * the address is the upper seven bits and the LSB is the "read/write" + * bit. Note that the {i2c_chip} address specified on the command + * line is not shifted up: e.g. a typical EEPROM memory chip may have + * an I2C address of 0x50, but the data put on the bus will be 0xA0 + * for write and 0xA1 for read. This "non shifted" address notation + * matches at least half of the data sheets :-/. + * + * {addr} is the address (or offset) within the chip. Small memory + * chips have 8 bit addresses. Large memory chips have 16 bit + * addresses. Other memory chips have 9, 10, or 11 bit addresses. + * Many non-memory chips have multiple registers and {addr} is used + * as the register index. Some non-memory chips have only one register + * and therefore don't need any {addr} parameter. + * + * The default {addr} parameter is one byte (.1) which works well for + * memories and registers with 8 bits of address space. + * + * You can specify the length of the {addr} field with the optional .0, + * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are + * manipulating a single register device which doesn't use an address + * field, use "0.0" for the address and the ".0" length field will + * suppress the address in the I2C data stream. This also works for + * successive reads using the I2C auto-incrementing memory pointer. + * + * If you are manipulating a large memory with 2-byte addresses, use + * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal). + * + * Then there are the unfortunate memory chips that spill the most + * significant 1, 2, or 3 bits of address into the chip address byte. + * This effectively makes one chip (logically) look like 2, 4, or + * 8 chips. This is handled (awkwardly) by #defining + * CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the + * {addr} field (since .1 is the default, it doesn't actually have to + * be specified). Examples: given a memory chip at I2C chip address + * 0x50, the following would happen... + * imd 50 0 10 display 16 bytes starting at 0x000 + * On the bus: A0 00 A1 ... + * imd 50 100 10 display 16 bytes starting at 0x100 + * On the bus: A2 00 A3 ... + * imd 50 210 10 display 16 bytes starting at 0x210 + * On the bus: A4 10 A5 ... + * This is awfully ugly. It would be nice if someone would think up + * a better way of handling this. + * + * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). */ #include @@ -51,8 +105,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); /* * Syntax: - * imd {i2c_chip} {addr}{.1, .2} {len} - * addr len + * imd {i2c_chip} {addr}{.0, .1, .2} {len} */ #define DISP_LINE_LEN 16 @@ -171,7 +224,7 @@ int do_i2c_nm (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* Write (fill) memory * * Syntax: - * imw {i2c_chip} {addr}{.1, .2} {data} [{count}] + * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] */ int do_i2c_mw (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { @@ -253,7 +306,7 @@ int do_i2c_mw (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* Calculate a CRC on memory * * Syntax: - * icrc32 {i2c_chip} {addr}{.1, .2} {count} + * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count} */ int do_i2c_crc (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { @@ -327,8 +380,8 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* Modify memory. * * Syntax: - * imm {i2c_chip} {addr}{.1, .2} - * inm {i2c_chip} {addr}{.1, .2} + * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} + * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} */ static int @@ -470,7 +523,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) /* * Syntax: - * iprobe {addr}{.1, .2} + * iprobe {addr}{.0, .1, .2} */ int do_i2c_probe(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { @@ -490,7 +543,7 @@ int do_i2c_probe(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* * Syntax: - * iloop {i2c_chip} {addr}{.1, .2} [{length}] [{delay}] + * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] * {length} - Number of bytes to read * {delay} - A DECIMAL number and defaults to 1000 uSec */ diff --git a/common/soft_i2c.c b/common/soft_i2c.c index 47bfeaf..f85d02a 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -33,7 +33,7 @@ #if defined(CONFIG_SOFT_I2C) -#define DEBUG_I2C +#define DEBUG_I2C /*----------------------------------------------------------------------- diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index dfc37c7..6e4bfcf 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -27,6 +27,14 @@ static void _i2c_bus_reset (void) { int i, status; + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out8 (IIC_STS, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out8 (IIC_EXTSTS, 0x8F); + __asm__ volatile ("eieio"); + /* * Get current state, reset bus * only if no transfers are pending. diff --git a/include/config_CANBT.h b/include/config_CANBT.h index d797f46..f0a3dcc 100644 --- a/include/config_CANBT.h +++ b/include/config_CANBT.h @@ -164,7 +164,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h index b4efca6..bc3eb99 100644 --- a/include/config_CPCI405.h +++ b/include/config_CPCI405.h @@ -240,7 +240,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ diff --git a/include/config_CPCIISER4.h b/include/config_CPCIISER4.h index 2bab3e1..a7ec1d4 100644 --- a/include/config_CPCIISER4.h +++ b/include/config_CPCIISER4.h @@ -168,7 +168,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ diff --git a/include/config_CPU86.h b/include/config_CPU86.h index 28f9033..115d1f9 100644 --- a/include/config_CPU86.h +++ b/include/config_CPU86.h @@ -332,7 +332,9 @@ /* environment is in EEPROM */ #define CFG_ENV_IS_IN_EEPROM 1 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_ENV_OFFSET 0 #define CFG_ENV_SIZE 2048 #endif diff --git a/include/config_DU405.h b/include/config_DU405.h index c4cbd34..6b191a7 100644 --- a/include/config_DU405.h +++ b/include/config_DU405.h @@ -194,7 +194,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ diff --git a/include/config_IP860.h b/include/config_IP860.h index b1a062d..2ed7c5c 100644 --- a/include/config_IP860.h +++ b/include/config_IP860.h @@ -85,7 +85,9 @@ # define CFG_I2C_SPEED 50000 # define CFG_I2C_SLAVE 0xFE # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ +# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_I2C | \ diff --git a/include/config_MHPC.h b/include/config_MHPC.h index 2f38167..1ae9bb3 100644 --- a/include/config_MHPC.h +++ b/include/config_MHPC.h @@ -95,6 +95,8 @@ # define CFG_I2C_SLAVE 0xFE # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ # define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CONFIG_BR0_WORKAROUND 1 diff --git a/include/config_MIP405.h b/include/config_MIP405.h index 69d15e1..9719863 100644 --- a/include/config_MIP405.h +++ b/include/config_MIP405.h @@ -230,9 +230,6 @@ #define CONFIG_BOARD_PRE_INIT -/* On Chip Memory location */ -#define OCM_DATA_ADDR 0xF0000000 - /* Peripheral Bus Mapping */ #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ @@ -245,8 +242,11 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */ -#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET diff --git a/include/config_OCRTC.h b/include/config_OCRTC.h index fb31045..6d8a842 100644 --- a/include/config_OCRTC.h +++ b/include/config_OCRTC.h @@ -197,7 +197,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ diff --git a/include/config_ORSG.h b/include/config_ORSG.h index 250de3b..000b640 100644 --- a/include/config_ORSG.h +++ b/include/config_ORSG.h @@ -197,7 +197,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ diff --git a/include/config_PIP405.h b/include/config_PIP405.h index ac9b592..2256f4b 100644 --- a/include/config_PIP405.h +++ b/include/config_PIP405.h @@ -225,10 +225,6 @@ #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/* On Chip Memory location */ -#define OCM_DATA_ADDR 0xF0000000 - /* Configuration Port location */ #define CONFIG_PORT_ADDR 0xF4000000 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 @@ -238,8 +234,11 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */ -#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET diff --git a/include/config_RPXClassic.h b/include/config_RPXClassic.h index 8eb528a..48420ca 100644 --- a/include/config_RPXClassic.h +++ b/include/config_RPXClassic.h @@ -147,7 +147,9 @@ # define CFG_I2C_SPEED 50000 # define CFG_I2C_SLAVE 0x34 # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ +# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) diff --git a/include/config_TQM8260.h b/include/config_TQM8260.h index fe9dcdb..dd1e108 100644 --- a/include/config_TQM8260.h +++ b/include/config_TQM8260.h @@ -203,7 +203,9 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_I2C) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include diff --git a/include/config_W7OLMC.h b/include/config_W7OLMC.h index 07469d8..dedae4f 100644 --- a/include/config_W7OLMC.h +++ b/include/config_W7OLMC.h @@ -255,7 +255,7 @@ #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x03 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/