From: Linus Torvalds Date: Thu, 2 Oct 2025 00:19:38 +0000 (-0700) Subject: Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=0f048c878ee32a4259dbf28e0ad8fd0b71ee0085;p=users%2Fjedix%2Flinux-maple.git Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ... --- 0f048c878ee32a4259dbf28e0ad8fd0b71ee0085 diff --cc Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 32c3b69ccf34,f0693b872cb6..51241c1293e3 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@@ -80,11 -80,12 +80,17 @@@ properties support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: | + Tegra256 has 8 generic I2C controllers. The controllers are similar to + the previous generations, but have a different parent clock and hence + the timing parameters are configured differently. + const: nvidia,tegra256-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. In addition to the features from + Tegra194, a SW mutex register is added to support use of the same I2C + instance across multiple firmwares. + const: nvidia,tegra264-i2c reg: maxItems: 1 @@@ -191,7 -192,7 +197,8 @@@ allOf contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra256-i2c + - nvidia,tegra264-i2c then: required: - resets diff --cc Documentation/devicetree/bindings/riscv/extensions.yaml index de41a6f074d3,5638297759df..543ac94718e8 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@@ -662,13 -662,25 +662,31 @@@ properties Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # MIPS + - const: xmipsexectl + description: + The MIPS extension for execution control as documented in + https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf + # SiFive + - const: xsfcease + description: + SiFive CEASE Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfcflushdlone + description: + SiFive L1D Cache Flush Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfpgflushdlone + description: + SiFive PGFLUSH Instruction Extensions for the power management. The + CPU will flush the L1D and enter the cease state after executing + the instruction. + - const: xsfvqmaccdod description: SiFive Int8 Matrix Multiplication Extensions Specification.