From: Jouni Högander Date: Wed, 29 May 2024 09:38:44 +0000 (+0300) Subject: drm/i915/psr: Add Early Transport status boolean into intel_psr X-Git-Tag: configfs-6.13-2024-11-19~902^2~20^2~170 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=0e3771f459ad84a286802ee22896f7a64a744f21;p=users%2Fhch%2Fconfigfs.git drm/i915/psr: Add Early Transport status boolean into intel_psr Currently we are purely relying on psr2_su_region_et_valid. Add new boolean value into intel_psr struct indicating whether Early Transport is enabled or not and use it instead of psr2_su_region_et_valid for getting Early Transport status information. Reviewed-by: Animesh Manna Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 52d0fd2bdc82..77609656317b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1706,6 +1706,7 @@ struct intel_psr { bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; + bool su_region_et_enabled; bool req_psr2_sdp_prior_scanline; u8 sink_sync_latency; ktime_t last_entry_attempt; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4b337bcd9c90..410b51f38d48 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -978,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0); } - if (psr2_su_region_et_valid(intel_dp)) + if (intel_dp->psr.su_region_et_enabled) val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; /* @@ -1771,6 +1771,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.dc3co_exit_delay = val; intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; + intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; intel_dp->psr.req_psr2_sdp_prior_scanline = crtc_state->req_psr2_sdp_prior_scanline; @@ -1927,6 +1928,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; + intel_dp->psr.su_region_et_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; }