From: wdenk <wdenk>
Date: Mon, 28 Oct 2002 00:09:18 +0000 (+0000)
Subject: Patch by Robert Schwebel, 27 Oct 2002:
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=0b8039cd07d395d2c3938909c67eb503f95e1a64;p=users%2Frw%2Fppcboot.git

Patch by Robert Schwebel, 27 Oct 2002:
XScale / csb226 updates (WIP)
---

diff --git a/CHANGELOG b/CHANGELOG
index cbeadd6..67021d5 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Modifications since 1.2.1:
 ======================================================================
 
+* Patch by Robert Schwebel, 27 Oct 2002:
+  XScale / csb226 updates (WIP)
+
 * ARM: Do not include BSS segment in the calculation of the size of
   the write-protected part of the flash memory.
 
diff --git a/README b/README
index ae5114b..96ca42b 100644
--- a/README
+++ b/README
@@ -1516,7 +1516,7 @@ Low Level (hardware related) configuration options:
 - CFG_INIT_RAM_ADDR:
 
 		Start address of memory area tha can be used for
-		initial data and stack; please note that this mus be
+		initial data and stack; please note that this must be
 		writable memory that is working WITHOUT special
 		initialization, i. e. you CANNOT use normal RAM which
 		will become available only after programming the
@@ -1831,7 +1831,7 @@ Some configuration options can be set using Environment Variables:
 		  variable to a value of "no" or "off" or "0".
 		  Alternatively, you can set it to a maximum upper
 		  address to use (PPCBoot will still check that it
-		  does not overwrite the PCBoot stack and data).
+		  does not overwrite the PPCBoot stack and data).
 
 		  For instance, when you have a system with 16 MB
 		  RAM, and want to reseve 4 MB from use by Linux,
@@ -2481,11 +2481,13 @@ this:
 	      :
 	      :
 	0x00FB FF20	Monitor Stack (Growing downward)
-	0x00FB FFAC	Board Info Data
+	0x00FB FFAC	Board Info Data and permanent copy of global data
 	0x00FC 0000	Malloc Arena
 	      :
 	0x00FD FFFF
 	0x00FE 0000	RAM Copy of Monitor Code
+	...		eventually: LCD or video framebuffer
+	...		eventually: pRAM (Protected RAM - unchanged by reset)
 	0x00FF FFFF	[End of RAM]
 
 
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
index d6ec08c..7befcc3 100644
--- a/board/csb226/config.mk
+++ b/board/csb226/config.mk
@@ -6,8 +6,11 @@
 # download areas is c800'0000
 #
 
-
-#TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3000000
+# This is the address where ppcboot lives in flash: 
 #TEXT_BASE = 0
 
+# FIXME: armboot does only work correctly when being compiled 
+# for the addresses _after_ relocation to RAM!! Otherwhise the 
+# .bss segment is assumed in flash...
+TEXT_BASE = 0xa1fe0000
+
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index cd6ed07..1335fd7 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -40,12 +40,12 @@ int board_init (void)
 	/* so we do _nothing_ here */
 
 	/* arch number of CSB226 board */
-	gd->bd->bi_arch_number = 89;
+	gd->bd->bi_arch_number = 0; 		/* FIXME */
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
 
-	return 1;
+	return 0;
 }
 
 int dram_init (void)
@@ -55,5 +55,5 @@ int dram_init (void)
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
-	return PHYS_SDRAM_1_SIZE;
+	return 0;
 }
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
index 68f5fcb..961d1bd 100644
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -27,7 +27,7 @@
 
 #include <common.h>
 
-#define FLASH_BANK_SIZE 0x2000000
+#define FLASH_BANK_SIZE 0x02000000
 #define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
 
 flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
@@ -50,6 +50,7 @@ ulong flash_init(void)
 	flash_info[i].size = FLASH_BANK_SIZE;
 	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
 	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	
         switch (i)
         {
            case 0:
diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S
index 5d80299..66b5a1a 100644
--- a/board/csb226/memsetup.S
+++ b/board/csb226/memsetup.S
@@ -31,7 +31,7 @@
 
 DRAM_SIZE:  .long   CFG_DRAM_SIZE
 
-// wait for coprocessor write complete
+/* wait for coprocessor write complete */
    .macro CPWAIT reg
    mrc  p15,0,\reg,c2,c0,0
    mov  \reg,\reg
@@ -39,12 +39,16 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
    .endm
 
 
+/*
+ * 	Memory setup
+ */
+
 .globl memsetup
 memsetup:
 
     mov      r10, lr
 
-    /* Set up GPIO pins first */
+	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
 	ldr		r1,	=CFG_GPSR0_VAL
@@ -106,563 +110,300 @@ memsetup:
 	ldr		r1,	=CFG_GAFR2_U_VAL
 	str		r1,   [r0]
 
-   // enable GPIO pins
-	ldr		r0,	=PSSR
+	ldr	r0,	=PSSR		/* enable GPIO pins */
 	ldr		r1,	=CFG_PSSR_VAL
 	str		r1,   [r0]
 
-   ldr    r3, =MSC1		    		// low - bank 2 Lubbock Registers / SRAM
-   ldr    r2, =CFG_MSC1_VAL			// high - bank 3 Ethernet Controller
-   str    r2, [r3]  				// need to set MSC1 before trying to write to the HEX LEDs
-   ldr    r2, [r3]  				// need to read it back to make sure the value latches (see MSC section of manual)
-
-   ldr    r1, =LED_BLANK
-   mov    r0, #0xFF
-   str    r0, [r1]    				// turn on hex leds
-
-loop:
-   ldr		r0, =0xB0070001
-   ldr    	r1, =_LED
-   str    	r0, [r1]    			// hex display
-
-/*********************************************************************
-    Initlialize Memory Controller
-	 The sequence below is based on the recommended init steps detailed
-	 in the EAS, chapter 5 (Chapter 10, Operating Systems Developers Guide)
-
-
-    pause for 200 uSecs- allow internal clocks to settle
-	 *Note: only need this if hard reset... doing it anyway for now
-*/
-
-	@ ---- Wait 200 usec
-	ldr r3, =OSCR       @ reset the OS Timer Count to zero
+//	ldr	r3,	=MSC1		/* low - bank 2 Lubbock Registers / SRAM */
+//	ldr	r2,	=CFG_MSC1_VAL	/* high - bank 3 Ethernet Controller */
+//	str	r2,	[r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
+//	ldr	r2,	[r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
+//
+//	ldr	r1,	=LED_BLANK
+//	mov	r0,	#0xFF
+//	str	r0,	[r1]		/* turn on hex leds */
+//
+//loop:
+//
+//   ldr	r0, =0xB0070001
+//   ldr    	r1, =_LED
+//   str    	r0, [r1]		/* hex display */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
 	mov r2, #0
 	str r2, [r3]
-	ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
 1:
 	ldr r2, [r3]
 	cmp r4, r2
 	bgt 1b
 
 mem_init:
-        @ get memory controller base address
-        ldr     r1,  =MEMC_BASE
 
-@****************************************************************************
-@  Step 1
-@
+        ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
 
-        @ write msc0, read back to ensure data latches
-        @
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+        /* MSC0: nCS(0,1)                                                   */
         ldr     r2,   =CFG_MSC0_VAL
         str     r2,   [r1, #MSC0_OFFSET]
-        ldr     r2,   [r1, #MSC0_OFFSET]
-
-        @ write msc1
+        ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */	
+        /* MSC1: nCS(2,3)                                                   */
         ldr     r2,  =CFG_MSC1_VAL
         str     r2,  [r1, #MSC1_OFFSET]
         ldr     r2,  [r1, #MSC1_OFFSET]
 
-        @ write msc2
+	/* MSC2: nCS(4,5)                                                   */
         ldr     r2,  =CFG_MSC2_VAL
         str     r2,  [r1, #MSC2_OFFSET]
         ldr     r2,  [r1, #MSC2_OFFSET]
 
-        @ write mecr
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
         ldr     r2,  =CFG_MECR_VAL
         str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET] 
 
-        @ write mcmem0
+	/* MCMEM0: Card Interface slot 0 timing                             */
         ldr     r2,  =CFG_MCMEM0_VAL
         str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
-        @ write mcmem1
+        /* MCMEM1: Card Interface slot 1 timing                             */
         ldr     r2,  =CFG_MCMEM1_VAL
         str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
-        @ write mcatt0
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
         ldr     r2,  =CFG_MCATT0_VAL
         str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
 
-        @ write mcatt1
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
         ldr     r2,  =CFG_MCATT1_VAL
         str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
 
-        @ write mcio0
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
         ldr     r2,  =CFG_MCIO0_VAL
         str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
 
-        @ write mcio1
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
         ldr     r2,  =CFG_MCIO1_VAL
         str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
 
-        @-------------------------------------------------------
-        @ 3rd bullet, Step 1
-        @
+	/* ---------------------------------------------------------------- */
+        /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+        /* ---------------------------------------------------------------- */
 
-        @ get the mdrefr settings
-        ldr     r3,  =CFG_MDREFR_VAL_100
 
-        @ extract DRI field (we need a valid DRI field)
-        @
-        ldr     r2,  =0xFFF
+	/* ---------------------------------------------------------------- */
+        /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+        /* ---------------------------------------------------------------- */
 
-        @ valid DRI field in r3
-        @
-        and     r3,  r3,  r2
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DIR field.                           */
 
-        @ get the reset state of MDREFR
-        @
+	ldr	r4,	=0x03ca4fff
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
         ldr     r4,  [r1, #MDREFR_OFFSET]
 
-        @ clear the DRI field
-        @
-        bic     r4,  r4,  r2
-
-        @ insert the valid DRI field loaded above
-        @
-        orr     r4,  r4,  r3
-
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
-
-        @ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@  Step 2
-@
-        /* This should be for SRAM, why is it commented out??? */
-
-        @ fetch sxcnfg value
-        @
-        @ldr     r2,  =0
-        @ write back sxcnfg
-        @str     r2,  [r1, #SXCNFG_OFFSET]
-
-//	@if sxcnfg=0, don't program for synch-static memory
-        @cmp     r2,  #0
-        @beq     1f
-
-        @program sxmrs
-        @ldr     r2,  =SXMRS_SETTINGS
-        @str     r2,  [r1, #SXMRS_OFFSET]
-
-
-@****************************************************************************
-@  Step 3
-@
-
-        @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-        @ clear the free-running clock bits
-        @ (clear K0Free, K1Free, K2Free
-        @
-        bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-        @ set K1RUN if bank 0 installed
-        @
-        orr   r4,  r4,  #0x00010000
-
-
-
-#ifdef THIS
-@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-@<!<!<!<!<!<!<!<!<!<!<!  Begin INSERT 1    <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-        @ Lubbock: Allow the user to select the {T/R/M} with predetermined
-        @   SDCLK.  Based on Table 3-1 in PXA250 and PXA210 Dev Man.
-        @
-        @  * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
-        @
-        @   S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)
-        @   S25, S26 used to provide all 200 MHz BIN values for Sabinal
-        @
-        @   S23: Force the halving of MemClk when deriving SDCLK[1]
-        @        DOT: no override  !DOT: halve (if not already forced half)
-//	@        *For certain MemClks, SDCLK's derivation is forced to be halved
-        @
-        @   S24: Run/Turbo.
-        @        DOT: Run mode   !DOT: Turbo mode
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-        @
-        @ Allow the user to control K1DB2 where applicable
-        @
-        @ Get the value of S23:          @ 1 = DOT (unity), 0 = !DOT (halve it)
-        @
-        @ DOT:   set K1DB2     (SDCLD = MemClk)
-        @ !DOT:  clear K1DB2   (SDCLK = MemClk/2)
-        @
-        @ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-        bl GET_S23                          @ r3, r2                    @ get the value of S23 in R0, i put the base adx of fpga in r3
-
-        cmp      r3, #0x0                 @ is !DOT?
-        orreq    r4, r4,  #0x00020000     @ SDClk[1] = MemClk/2
-        bicne    r4, r4,  #0x00020000     @ SDClk[1] = MemClk
-
-        @
-        @ Next, we need to look for S25,S26 selections that necessitate the
-        @  halving of MemClk to derive SDCLK[1]: (S25,S26)={03-0C, 10-13}
-        @ Override above S23-based selection accordingly.
-        @
-        ldr r2, =FPGA_REGS_BASE_PHYSICAL
-        bl  GET_S25                           @ r0, r2
-                                       @ get the value of S25 in R0, i put the base adx of fpga in r2
-
-
-
-        ldr r2, =FPGA_REGS_BASE_PHYSICAL
-        BL  GET_S26                              @ r3, r2
-                                      @ get the value of S26 in R1, i put the base adx of fpga in r2
-
-        orr     r0, r0, r3               @ concatenate S25 & S26 vals
-        and     r0, r0, #0xFF
-
-        @ Set K1DB2 for the frequencies that require it
-        @
-        cmp     r0, #0x03
-        cmpne   r0, #0x04
-        cmpne   r0, #0x05
-        cmpne   r0, #0x06
-        cmpne   r0, #0x07
-        cmpne   r0, #0x08
-        cmpne   r0, #0x09
-        cmpne   r0, #0x0A
-        cmpne   r0, #0x0B
-        cmpne   r0, #0x0C
-        cmpne   r0, #0x10
-        cmpne   r0, #0x11
-        cmpne   r0, #0x12
-        cmpne   r0, #0x13
-        orreq   r4, r4,  #0x00020000     @ SDCLK[1] = (MemClk)/2 for 03 - 0C @ 10 - 13
-
-        @
-        @ *Must make MSC0&1 adjustments now for MEMClks > 100MHz.
-        @
-        @ Adjust MSC0 for MemClks > 100 MHz
-        @
-        ldreq   r0,   [r1, #MSC0_OFFSET]
-        ldreq   r3,   =0x7F007F00
-        biceq   r0,   r0, r3                @ clear MSC0[14:12, 11:8] (RRR, RDN)
-        ldreq   r3,   =0x46004600
-        orreq   r0,   r0, r3                @ set   MSC0[14, 10:9]  (doubling RRR, RDN)
-        streq   r0,   [r1, #MSC0_OFFSET]
-        ldreq   r0,   [r1, #MSC0_OFFSET]    @ read it back to ensure that the data latches
-
-        @
-        @ Adjust MSC1.LH for MemClks > 100 MHz
-        @
-        ldreq   r0,   [r1, #MSC1_OFFSET]
-        ldreq   r3,   =0x7FF0
-        biceq   r0,   r0, r3               @ clear MSC1[14:12, 11:8, 7:4] (RRR, RDN, RDF)
-        ldreq   r3,   =0x4880
-        orreq   r0,   r0, r3               @ set   MSC1[14, 11, 7]  (doubling RRR, RDN, RDF)
-        streq   r0,   [r1, #MSC1_OFFSET]
-        ldreq   r0,   [r1, #MSC1_OFFSET]   @ read it back to ensure that the data latches
-
-        @                                                                   @
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-#endif
+	ldr	r4,	=0x03ca4030
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr	r4,	[r1, #MDREFR_OFFSET]
 
-@<!<!<!<!<!<!<!<!<!<!<!    End INSERT 1    <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
+        /* Note: preserve the mdrefr value in r4                            */
 
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
-        ldr     r4,  [r1, #MDREFR_OFFSET]
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
 
-        @ deassert SLFRSH
-        @
-        bic     r4,  r4,  #0x00400000
+	/* Initialize SXCNFG register. Assert the enable bits               */
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
 
-        @ assert E1PIN
-        @
-        orr     r4,  r4,  #0x00008000
+	/* FIXME: we use async mode for now                                 */
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
-        ldr     r4,  [r1, #MDREFR_OFFSET]
-        nop
-        nop
 
+        /* ---------------------------------------------------------------- */
+        /* Step 4: Initialize SDRAM                                         */
+        /* ---------------------------------------------------------------- */
 
-@****************************************************************************
-@  Step 4
-@
+	/* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure      */
+	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 
-        @ fetch platform value of mdcnfg
-        @
-        ldr     r2,  =CFG_MDCNFG_VAL
+	orr	r4,	r4,	#(MDREFR_K1RUN|MDREFR_K2RUN|MDREFR_K0RUN)
 
-        @ disable all sdram banks
-        @
-        bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-        bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
 
-        @ program banks 0/1 for bus width
-        @
-        bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
 
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
 
-        @ write initial value of mdcnfg, w/o enabling sdram banks
-        @
-        str     r2,  [r1, #MDCNFG_OFFSET]
+	bic	r4,	r4,	#(MDREFR_SLFRSH)
 
-@ ****************************************************************************
-@  Step 5
-@
+        str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+        ldr     r4,     [r1, #MDREFR_OFFSET]
 
-        @ pause for 200 uSecs
-        @
-    	ldr r3, =OSCR   @reset the OS Timer Count to zero
-    	mov r2, #0
-	    str r2, [r3]
-	    ldr r4, =0x300			@really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
 
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
 
-@****************************************************************************
-@  Step 6
-@
+	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
 
-	mov    r0, #0x78			@turn everything off
-	mcr    p15, 0, r0, c1, c0, 0		@(caches off, MMU off, etc.)
+        str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+        ldr     r4,     [r1, #MDREFR_OFFSET]
 
 
-@ ****************************************************************************
-@  Step 7
-@
-        @ Access memory *not yet enabled* for CBR refresh cycles (8)
-        @ - CBR is generated for all banks
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
 
-	    ldr     r2, =CFG_DRAM_BASE
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
+        str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+        ldr     r4,     [r1, #MDCNFG_OFFSET]
 
-@ ****************************************************************************
-@  Step 8: NOP (enable dcache if you wanna... we dont)
-@
 
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
 
-@ ****************************************************************************
-@  Step 9
-@
-
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
 
-        @get memory controller base address
-        @
-        ldr     r1,  =MEMC_BASE
 
-        @fetch current mdcnfg value
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
 
-        @enable sdram bank 0 if installed (must do for any populated bank)
-        @
-        orr     r3,  r3,  #MDCNFG_DE0
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
 
-        @write back mdcnfg, enabling the sdram bank(s)
-        @
-        str     r3,  [r1, #MDCNFG_OFFSET]
 
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
 
-@****************************************************************************
-@  Step 10
-@
+	ldr	r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str	r3, [r1, #MDCNFG_OFFSET]
+	
+	/* Step 4h: Write MDMRS.                                            */
 
-        @ write mdmrs
-        @
         ldr     r2,  =CFG_MDMRS_VAL
         str     r2,  [r1, #MDMRS_OFFSET]
 
 
-@****************************************************************************
-@  Step 11: Final Step
-@
+	/* We are finished with Intel's memory controller initialisation    */
+
 
-@INITINTC
-        @********************************************************************
-        @ Disable (mask) all interrupts at the interrupt controller
-        @
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
 
-        @ clear the interrupt level register (use IRQ, not FIQ)
-        @
-        mov     r1, #0
+initirqs:
+
+        mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
         ldr     r2,  =ICLR
         str     r1,  [r2]
 
-        @ mask all interrupts at the controller
-        @
-        ldr     r2,  =ICMR
+        ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
         str     r1,  [r2]
 
 
-@INITCLKS
-        @ ********************************************************************
-        @ Disable the peripheral clocks, and set the core clock
-        @ frequency (hard-coding at 398.12MHz for now).
-        @
+        /* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+        /* ---------------------------------------------------------------- */
+
+initclks: 
 
-		@ Turn Off ALL on-chip peripheral clocks for re-configuration
-		@ *Note: See label 'ENABLECLKS' for the re-enabling
-		@
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
         ldr     r1,  =CKEN
         mov     r2,  #0
         str     r2,  [r1]
 
 
-        @ default value in case no valid rotary switch setting is found
-        ldr     r2, =(CCCR_L27 | CCCR_M2 | CCCR_N10)        @ DEFAULT: {200/200/100}
-
+        /* default value in case no valid rotary switch setting is found    */
+        ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
 
-        @... and write the core clock config register
-        @
+        /* ... and write the core clock config register                     */
         ldr     r1,  =CCCR
         str     r2,  [r1]
 
-/*
-	@ enable the 32Khz oscillator for RTC and PowerManager
-        @
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
         ldr     r1,  =OSCC
         mov     r2,  #OSCC_OON
         str     r2,  [r1]
 
-
-        @ NOTE:  spin here until OSCC.OOK get set,
-        @        meaning the PLL has settled.
-        @
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
 60:
         ldr     r2, [r1]
         ands    r2, r2, #1
         beq     60b
-*/
-
-@OSCC_OON_DONE
-
-
-#ifdef  A0_COTULLA
-    @****************************************************************************
-    @ !!! Take care of A0 Errata Sighting #4 --
-    @ after a frequency change, the memory controller must be restarted
-    @
-
-        @ get memory controller base address
-        ldr     r1,  =MEMC_BASE
-
-        @ get the current state of MDREFR
-        @
-        ldr     r2,  [r1, #MDREFR_OFFSET]
-
-        @ clear E0PIN, E1PIN
-        @
-        bic     r3,  r2,  #(MDREFR_E0PIN | MDREFR_E1PIN)
-
-        @ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
-        @
-        str     r3,  [r1, #MDREFR_OFFSET]
-
-        @ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
-        @
-        str     r2,  [r1, #MDREFR_OFFSET]
-
-        @ get the current state of MDCNFG
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ disable all SDRAM banks
-        @
-        bic     r3,  r3,  #(MDCNFG_DE0 | MDCNFG_DE1)
-        bic     r3,  r3,  #(MDCNFG_DE2 |  MDCNFG_DE3)
-
-        @ write back MDCNFG
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-	    @ Access memory not yet enabled for CBR refresh cycles (8)
-        @ - CBR is generated for *all* banks
-	    ldr     r2, =CFG_DRAM_BASE
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-
-        @ fetch current mdcnfg value
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ enable sdram bank 0 if installed
-        @
-        orr     r3,  r3,  #MDCNFG_DE0
-
-        @ write back mdcnfg, enabling the sdram bank(s)
-        @
-        str     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ write mdmrs
-        @
-        ldr     r2,  =CFG_MDMRS_VAL
-        str     r2,  [r1, #MDMRS_OFFSET]
 
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+        /* ---------------------------------------------------------------- */
 
-
-    //    @ errata: don't enable auto power-down
-        @ get current value of mdrefr
-        @ldr     r3,  [r1, #MDREFR_OFFSET]
-        @ enable auto-power down
-        @orr     r3,  r3,  #MDREFR_APD
-        @write back mdrefr
-        @str     r3,  [r1, #MDREFR_OFFSET]
-
-#endif A0_Cotulla
-
-
-  ldr     r0, =0x000C0dE3
-  ldr    	r1, =_LED
-  str    	r0, [r1]    		// hex display
-
-@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
-@ ^%^%^%^%^%^%^%^%^%   above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
-@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
-
-
-	// Save SDRAM size
+	/* Save SDRAM size                                                  */
 	ldr	r1, =DRAM_SIZE
 	str	r8, [r1]
 
-	ldr	r0, =0xC0DE0006
-	ldr	r1, =_LED
-	str	r0, [r1]    		// hex display
-
-	// Interrupt init
-	// Mask all interrupts
-	ldr	r0, =ICMR		// enable no sources
+	/* Interrupt init: Mask all interrupts                              */
+	ldr	r0, =ICMR			/* enable no sources        */
 	mov	r1, #0
 	str	r1, [r0]
 
+	/* FIXME */
+
 #define NODEBUG
 #ifdef NODEBUG
 	//Disable software and data breakpoints
@@ -677,76 +418,11 @@ mem_init:
 
 #endif
 
-	ldr     r0, =0xBEEF001D
-    ldr    	r1, =_LED
-    str    	r0, [r1]    		// hex display
-
-	mov	pc, r10
-
-@ End memsetup
-
-#ifdef gargelpu
-@ %%%%%%%%%%%   Useful subroutines
-GET_S23:
-    @ This macro will read S23 and return its value in r3
-    @ r2 contains the base address of the Lubbock user registers
-    ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-    //@ read S23's value
-    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r3, r3, #0x200
-
-    @ get bit into position 0
-    mov     r3, r3, LSR #9
-
-    mov     pc, lr
-@ End GET_S23
-
-
-GET_S24:
-    @ This macro will read S24 and return its value in r0
-    @ r2 contains the base address of the Lubbock user registers
-    ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-    //@ read S24's value
-    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r0, r0, #0x100
-
-    @ get bit into position 0
-    mov     r0, r0, LSR #8
-
-    mov     pc, lr
-@ End GET_S23
+        /* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+        /* ---------------------------------------------------------------- */
 
-
-GET_S25:
-    @ This macro will read rotary S25 and return its value in r0
-    @ r2 contains the base address of the Lubbock user registers
-    @ read the user switches register
-    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r0, r0, #0xF0
-
-    mov     pc, lr
-@ End subroutine
-
-
-GET_S26:
-    @ This macro will read rotary S26 and return its value in r3
-    @ r2 contains the base address of the Lubbock user registers
-    @ read the user switches register
-    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r3, r3, #0x0F
+endmemsetup:
 
     mov     pc, lr
-@ End subroutine GET_S26
-
-#endif /* gargelpu */
 
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index 03f228d..795ccd5 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -104,19 +104,11 @@
 #define VIDEO_LINE_LEN		(VIDEO_COLS*VIDEO_PIXEL_SIZE)	/* Number of bytes per line */
 #define VIDEO_BURST_LEN		(VIDEO_COLS/8)
 
-#if 0-0
-#ifdef VIDEO_MODE_YUYV
-#define VIDEO_BG_COL 	0x80108010	/* Background color in YUYV format */
-#else
-#define VIDEO_BG_COL 	0x00000000	/* Background color in RGB format */
-#endif
-#else
 #ifdef VIDEO_MODE_YUYV
 #define VIDEO_BG_COL 	0x80D880D8	/* Background color in YUYV format */
 #else
 #define VIDEO_BG_COL 	0xF8F8F8F8	/* Background color in RGB format */
 #endif
-#endif /* 0-0 */
 
 /************************************************************************/
 /* ** FONT AND LOGO DATA						*/
@@ -495,12 +487,8 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
 }
 
 static void inline video_mode_addentry (VRAM * vr,
-										int Hx,
-										int Vx,
-										int Fx,
-										int Bx,
-										int VDS,
-										int INT, int LCYC, int LP, int LST)
+	int Hx, int Vx, int Fx, int Bx,
+	int VDS, int INT, int LCYC, int LP, int LST)
 {
 	vr->hx = Hx;
 	vr->vx = Vx;
@@ -816,7 +804,7 @@ static void video_ctrl_init (void *memptr)
 
 	/* Start of frame buffer (even and odd frame, to make it working with */
 	/* any selected active set) */
-	debug ("[VIDEO CTRL] Setting frame address...\n");
+	debug ("[VIDEO CTRL] Setting frame buffer address...\n");
 	immap->im_vid.vid_vfaa1 =
 		immap->im_vid.vid_vfaa0 = (u32) video_fb_address;
 	immap->im_vid.vid_vfba1 =
diff --git a/cpu/xscale/cpu.c b/cpu/xscale/cpu.c
index 5e6a7e7..6a3c24d 100644
--- a/cpu/xscale/cpu.c
+++ b/cpu/xscale/cpu.c
@@ -38,6 +38,10 @@ int cpu_init (void)
 	/*
 	 * setup up stack if necessary
 	 */
+/*
+
+  FIXME: the stack is _below_ the uboot code!!
+
 #ifdef CONFIG_USE_IRQ
 	IRQ_STACK_START = _armboot_end +
 			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
@@ -46,6 +50,7 @@ int cpu_init (void)
 #else
 	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
 #endif
+*/
 	return (0);
 }
 
diff --git a/cpu/xscale/start.S b/cpu/xscale/start.S
index e491e26..8700d1a 100644
--- a/cpu/xscale/start.S
+++ b/cpu/xscale/start.S
@@ -53,16 +53,12 @@ _fiq:			.word fiq
 
 
 /*
- *************************************************************************
- *
  * Startup Code (reset vector)
  *
  * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
+ * - relocate armboot to ram
+ * - setup stack
+ * - jump to second stage
  */
 
 /*
@@ -95,6 +91,13 @@ _armboot_end:
 _armboot_real_end:
 	.word 0x0badc0de
 
+/*
+ * We relocate uboot to this address (end of RAM - 128 KiB)
+ */
+.globl _uboot_reloc
+_uboot_reloc:
+	.word CFG_DRAM_BASE + CFG_DRAM_SIZE - CFG_MONITOR_LEN
+
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -108,52 +111,39 @@ FIQ_STACK_START:
 #endif
 
 
-/*
- * the actual reset code
- */
+/****************************************************************************/
+/*                                                                          */
+/* the actual reset code                                                    */
+/*                                                                          */
+/****************************************************************************/
 
 reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
+	mrs	r0,cpsr			/* set the cpu to SVC32 mode        */
+	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)       */
 	orr	r0,r0,#0x13
 	msr	cpsr,r0
 
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifdef CONFIG_INIT_CRITICAL
-	bl	cpu_init_crit
-#endif
+	bl	cpu_init_crit		/* we do sys-critical inits         */
 
-relocate:
-	/*
-	 * relocate armboot to RAM
-	 */
+relocate:				/* relocate ppcboot to RAM          */
 	adr	r0, _start		/* r0 <- current position of code */
 	ldr	r2, _armboot_start
 	ldr	r3, _armboot_end
 	sub	r2, r3, r2		/* r2 <- size of armboot */
-	ldr	r1, _TEXT_BASE		/* r1 <- destination address */
+/*	ldr	r1, _uboot_reloc	/* r1 <- destination address        */
+	ldr	r1, _TEXT_BASE
 	add	r2, r0, r2		/* r2 <- source end address */
 
-	/*
-	 * r0 = source address
-	 * r1 = target address
-	 * r2 = source end address
-	 */
 copy_loop:
-	ldmia	r0!, {r3-r10}
-	stmia	r1!, {r3-r10}
-	cmp	r0, r2
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */ 
 	ble	copy_loop
 
-	/* set up the stack */
-	ldr	r0, _armboot_end
-	add	r0, r0, #CONFIG_STACKSIZE
+	/* Set up the stack                                                 */
+	ldr	r0, _uboot_reloc	/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
+					/* FIXME: bdinfo should be here     */
 	sub	sp, r0, #12		/* leave 3 words for abort-stack */
 
 	ldr	pc, _start_armboot
@@ -161,46 +151,40 @@ copy_loop:
 _start_armboot:	.word start_armboot
 
 
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
+/****************************************************************************/
+/*                                                                          */
+/* CPU_init_critical registers                                              */
+/*                                                                          */
+/* - setup important registers                                              */
+/* - setup memory timing                                                    */
+/*                                                                          */
+/****************************************************************************/
 
-/* Interupt-Controller base address */
+	/* Interrupt-Controller base address                                */
 IC_BASE:	   .word	   0x40d00000
 #define ICMR	0x04
 
-
-/* FIXME RSRR doesn't exist on the PXA */
 /* Reset-Controller */
 RST_BASE:	.word   0x40f00030
-#define RSRR	0x00
 #define RCSR	0x00
 
 
-/* Clocks */
+	/* Clock Manager Registers                                          */
 CC_BASE:		.word	0x41300000
 #define CCCR    0x00
-
 cpuspeed:	.word   CFG_CPUSPEED
 
+	/* RS: ???                                                          */ 
 	.macro CPWAIT
     mrc  p15,0,r0,c2,c0,0
 	mov  r0,r0
 	sub  pc,pc,#4
 	.endm
 
+
 cpu_init_crit:
-	/*
-	 * mask all IRQs
-	 */
+
+	/* mask all IRQs                                                    */
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
 	str	r1, [r0, #ICMR]
@@ -219,41 +203,39 @@ cpu_init_crit:
 	bl	memsetup
 	mov	lr,	ip
 
-	/*
-	 * disable MMU stuff and enable I-cache
-	 */
-	ldr	r0, =0x2001			        // enable access to all coprocessors
+	/* Memory interfaces are working. Disable MMU and enable I-cache.   */
+
+	ldr	r0, =0x2001		/* enable access to all coproc.     */
 	mcr	p15, 0, r0, c15, c1, 0
     CPWAIT
 
-	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
+	mcr	p15, 0, r0, c7, c10, 4	/* drain the write & fill buffers   */
     CPWAIT
 
-	mcr	p15, 0, r0, c7, c7, 0		// flush Icache, Dcache and BTB
+	mcr	p15, 0, r0, c7, c7, 0	/* flush Icache, Dcache and BTB     */
     CPWAIT
 
-	mcr	p15, 0, r0, c8, c7, 0		// flush instuction and data TLBs
+	mcr	p15, 0, r0, c8, c7, 0	/* flush instuction and data TLBs   */
     CPWAIT
 
-	// Enable the Icache
+	/* Enable the Icache                                                */
+/*
 	mrc	p15, 0, r0, c1, c0, 0
 	orr	r0, r0, #0x1800
 	mcr	p15, 0, r0, c1, c0, 0
     CPWAIT
-
+*/
 	mov	pc, lr
 
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
 
-@
-@ IRQ stack frame.
-@
+/****************************************************************************/
+/*                                                                          */
+/* Interrupt handling                                                       */
+/*                                                                          */
+/****************************************************************************/
+
+/* IRQ stack frame                                                          */
+
 #define S_FRAME_SIZE	72
 
 #define S_OLD_R0	68
@@ -278,37 +260,38 @@ cpu_init_crit:
 
 #define MODE_SVC 0x13
 
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
+	/* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	stmia	sp, {r0 - r12}			/* Calling r0-r12           */
 	add     r8, sp, #S_PC
 
 	ldr	r2, _armboot_end
 	add	r2, r2, #CONFIG_STACKSIZE
 	sub	r2, r2, #8
-	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+	ldmia	r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
+	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC           */
 
 	add	r5, sp, #S_SP
 	mov	r1, lr
-	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
+	stmia	r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 	mov	r0, sp
 	.endm
 
+
+	/* use irq_save_user_regs / irq_restore_user_regs for                */
+	/* IRQ/FIQ handling                                                  */
+
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	stmia	sp, {r0 - r12}			/* Calling r0-r12            */
 	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
+	stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
+	str     lr, [r8, #0]                    /* Save calling PC           */
 	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
+	str     r6, [r8, #4]                    /* Save CPSR                 */
+	str     r0, [r8, #8]                    /* Save OLD_R0               */
 	mov	r0, sp
 	.endm
 
@@ -343,9 +326,13 @@ cpu_init_crit:
 	ldr	sp, FIQ_STACK_START
 	.endm
 
-/*
- * exception handlers
- */
+
+/****************************************************************************/
+/*                                                                          */
+/* exception handlers                                                       */
+/*                                                                          */
+/****************************************************************************/
+
 	.align  5
 undefined_instruction:
 	get_bad_stack
@@ -388,9 +375,8 @@ irq:
 	.align	5
 fiq:
 	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl 	do_fiq
+	irq_save_user_regs		/* someone ought to write a more    */
+	bl 	do_fiq			/* effiction fiq_save_user_regs     */ 
 	irq_restore_user_regs
 
 #else
@@ -420,6 +406,7 @@ reset_cpu:
 	mov	r1, #0x0			@ set bit 3-0 ...
 	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
 	mov	r1, #0x1
-	str	r1, [r0, #RSRR]			@ and perform reset
+	str	r1, [r0, #RCSR]			@ and perform reset
 	*/
 	b	reset_cpu			@ silly, but repeat endlessly
+
diff --git a/include/asm-arm/arch-xscale/pxa-regs.h b/include/asm-arm/arch-xscale/pxa-regs.h
index 3bc0751..c17d901 100644
--- a/include/asm-arm/arch-xscale/pxa-regs.h
+++ b/include/asm-arm/arch-xscale/pxa-regs.h
@@ -1095,8 +1095,20 @@ typedef void            (*ExcpHndlr) (void) ;
 #define MDCNFG_DE2      0x00010000
 #define MDCNFG_DE3      0x00020000
 #define MDCNFG_DWID0    0x00000004
+
 #define MDREFR_E0PIN    0x00001000
+#define MDREFR_K0RUN	0x00002000
+#define MDREFR_K0DB2	0x00004000
 #define MDREFR_E1PIN    0x00008000
+#define MDREFR_K1RUN	0x00010000
+#define MDREFR_K1DB2	0x00020000
+#define MDREFR_K2RUN	0x00040000
+#define MDREFR_K2DB2	0x00080000
+#define MDREFR_APD	0x00100000
+#define MDREFR_SLFRSH	0x00400000
+#define MDREFR_K0FREE	0x00800000
+#define MDREFR_K1FREE	0x01000000
+#define MDREFR_K2FREE	0x02000000
 
 #define MDCNFG_OFFSET   0x0
 #define MDREFR_OFFSET   0x4
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index f990721..56537ac 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -35,7 +35,7 @@
  * If we are developing, we might want to start ppcboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-#undef CONFIG_INIT_CRITICAL		/* undef for developing */
+#define CONFIG_INIT_CRITICAL		/* undef for developing */
 
 /*
  * High Level Configuration Options
@@ -46,14 +46,6 @@
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
 					/* for timer/console/ethernet       */
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are 
- * used for the RAM copy of the ppcboot code
- *
- + FIXME: the documentation says that this has to be CFG_MALLOC_LEN ???
- */
-#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
-
 /*
  * Hardware drivers
  */
@@ -66,7 +58,7 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_BAUDRATE		19200
 
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_NET)
 
@@ -79,7 +71,7 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		192.168.1.56
 #define CONFIG_SERVERIP		192.168.1.2
-#define CONFIG_BOOTCOMMAND	"FIXME"
+#define CONFIG_BOOTCOMMAND	""
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
@@ -89,6 +81,14 @@
 /*
  * Miscellaneous configurable options
  */
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are 
+ * used for the RAM copy of the uboot code
+ *
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
 #define CFG_LONGHELP				/* undef to save memory         */
 #define CFG_PROMPT		"=> "		/* Monitor Command Prompt       */
 #define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
@@ -101,12 +101,20 @@
 
 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR           0xa8000000      /* default load address */ 
+#define CFG_LOAD_ADDR           0xa7fe0000      /* default load address */ 
 						/* RS: where is this documented? */
+						/* RS: is this where ppcboot is  */
+						/* RS: relocated to in RAM?      */
 
 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 						/* RS: the oscillator is actually 3680130?? */
 #define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+						/* 0101000001 */
+						/*      ^^^^^ Memory Speed 99.53 MHz         */
+						/*    ^^      Run Mode Speed = 2x Mem Speed  */
+						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */ 
+
+#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
 
                                                 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -132,58 +140,60 @@
 #define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
 #define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
+#define CFG_DRAM_SIZE		0x02000000	 
 
 #define CFG_FLASH_BASE          PHYS_FLASH_1
 
-/* #define FPGA_REGS_BASE_PHYSICAL 0x08000000 */ /* we don't need this on CSB226...? */
-
 /*
  * GPIO settings
  */
-#define CFG_GPSR0_VAL       0x00008000
-#define CFG_GPSR1_VAL       0x00FC0382
-#define CFG_GPSR2_VAL       0x0001FFFF
-#define CFG_GPCR0_VAL       0x00000000
+#define CFG_GPSR0_VAL       0xFFFFFFFF
+#define CFG_GPSR1_VAL       0xFFFFFFFF
+#define CFG_GPSR2_VAL       0xFFFFFFFF
+#define CFG_GPCR0_VAL       0x08022080
 #define CFG_GPCR1_VAL       0x00000000
 #define CFG_GPCR2_VAL       0x00000000
-#define CFG_GPDR0_VAL       0x0060A800
-#define CFG_GPDR1_VAL       0x00FF0382
-#define CFG_GPDR2_VAL       0x0001C000
-#define CFG_GAFR0_L_VAL     0x98400000
-#define CFG_GAFR0_U_VAL     0x00002950
-#define CFG_GAFR1_L_VAL     0x000A9558
-#define CFG_GAFR1_U_VAL     0x0005AAAA
-#define CFG_GAFR2_L_VAL     0xA0000000
+#define CFG_GPDR0_VAL       0xCD82A858
+#define CFG_GPDR1_VAL       0xFCFFAB80
+#define CFG_GPDR2_VAL       0x0001FFFF
+#define CFG_GAFR0_L_VAL     0x80000000
+#define CFG_GAFR0_U_VAL     0xA5254010
+#define CFG_GAFR1_L_VAL     0x599A9550
+#define CFG_GAFR1_U_VAL     0xAAA5AAAA
+#define CFG_GAFR2_L_VAL     0xAAAAAAAA
 #define CFG_GAFR2_U_VAL     0x00000002
 
+/* FIXME: set GPIO_RER/FER */
+
 #define CFG_PSSR_VAL        0x20
 
 /*
  * Memory settings
  */
-#define CFG_MSC0_VAL        0x23F223F2
-#define CFG_MSC1_VAL        0x3FF1A441
-#define CFG_MSC2_VAL        0x7FF17FF1
-#define CFG_MDCNFG_VAL      0x00001AC9
-#define CFG_MDREFR_VAL      0x000BC018
-#define CFG_MDREFR_VAL_100  0x00018018
-#define CFG_MDMRS_VAL       0x00000000
+#define CFG_MSC0_VAL        0x2EF025D0
+#define CFG_MSC1_VAL        0x00003F64
+#define CFG_MSC2_VAL        0x00000000
+#define CFG_MDCNFG_VAL      0x09a909a9
+#define CFG_MDREFR_VAL      0x03ca0030
+/* #define CFG_MDREFR_VAL_100  ??? */
+#define CFG_MDMRS_VAL       0x00220022
 
 /*
  * PCMCIA and CF Interfaces
  */
 #define CFG_MECR_VAL        0x00000000
-#define CFG_MCMEM0_VAL      0x00010504
-#define CFG_MCMEM1_VAL      0x00010504
-#define CFG_MCATT0_VAL      0x00010504
-#define CFG_MCATT1_VAL      0x00010504
-#define CFG_MCIO0_VAL       0x00004715
-#define CFG_MCIO1_VAL       0x00004715
+#define CFG_MCMEM0_VAL      0x00000000
+#define CFG_MCMEM1_VAL      0x00000000
+#define CFG_MCATT0_VAL      0x00000000
+#define CFG_MCATT1_VAL      0x00000000
+#define CFG_MCIO0_VAL       0x00000000
+#define CFG_MCIO1_VAL       0x00000000
 
+/*
 #define _LED        0x08000010
 #define LED_BLANK  (0x08000040)
+*/
 
 /*
  * FLASH and environment organization
@@ -195,28 +205,9 @@
 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
 
-/* FIXME */
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
 					/* Addr of Environment Sector       */
 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
 
-
-/*
- * FPGA Offsets
- */
-/*
-#define WHOAMI_OFFSET           0x00
-#define HEXLED_OFFSET           0x10
-#define BLANKLED_OFFSET         0x40
-#define DISCRETELED_OFFSET      0x40
-#define CNFG_SWITCHES_OFFSET    0x50
-#define USER_SWITCHES_OFFSET    0x60
-#define MISC_WR_OFFSET          0x80
-#define MISC_RD_OFFSET          0x90
-#define INT_MASK_OFFSET         0xC0
-#define INT_CLEAR_OFFSET        0xD0
-#define GP_OFFSET               0x100
-*/
-
 #endif  /* __CONFIG_H */