From: wdenk <wdenk>
Date: Sun, 7 Oct 2001 21:49:04 +0000 (+0000)
Subject: Fix memory controller initialization for ICU862
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=09a7b8beb9545ee81f0b5c59354dba7ca98953ce;p=users%2Frw%2Fppcboot.git

Fix memory controller initialization for ICU862
---

diff --git a/CHANGELOG b/CHANGELOG
index 5f0a23b..da29766 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -56,6 +56,8 @@ To do:
 Modifications for 1.0.6:
 ======================================================================
 
+* Fix memory controller initialization for ICU862 board
+
 * Patch by Stefan Roese, 19 Sep 2001:
 - Watchdog support for ppc4xx added.
 - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c
index 9d7c9bb..00137cc 100644
--- a/board/icu862/icu862.c
+++ b/board/icu862/icu862.c
@@ -40,41 +40,43 @@
 
 /* ------------------------------------------------------------------------- */
 
-/* 40x2MHz tables */
+#define _not_used_	0xffffffff
+
 const uint sdram_table[]=
-{ 0x0e06fc04, 0x11acfc04, 0xefa98c00, 0x1ff77c47,
-  0xeeeabc35, 0x11b57fff, 0xffffffff, 0xffffffff,
-  0x0e06fc04, 0x10adfc00, 0xf0affc00, 0xf0affc00,
-  0xe1bbfc00, 0x1ff77c47, 0xffffffff, 0xffffffff,
-#if 0
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-#else
-  0xffffffff, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
-  0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
-#endif
-  0x0e26bc04, 0x01b93c00, 0x1ff77c47, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0e06bc04, 0x10ad7c00, 0xf0affc00, 0xf0affc00,
-  0xe1bbbc04, 0x1ff77c47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xfffffc04,
-  0x0ee27c04, 0x10a0fc84, 0xf0a0fc04, 0xf0a0fc84,
-  0xf1b5fc07, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xfffffc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-#define MAMR_VALUE	0x27904111
-#define MCR_INIT	0x8000222f
-#define MAR_VALUE	0x00000088
-#define MCR_L_M_R	0x80002105
-#define MPTPR_VALUE	0x0200
-
-#define OR1_VALUE	0xfe000900
-#define BR1_VALUE	0x00000081
+{
+        /* single read. (offset 0 in upm RAM) */
+        0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+        0x1ff77c47,
 
-/* ------------------------------------------------------------------------- */
+        /* MRS initialization (offset 5) */
+
+        0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+        /* burst read. (offset 8 in upm RAM) */
+        0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+        0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+        _not_used_, _not_used_, _not_used_, _not_used_,
+        _not_used_, _not_used_, _not_used_, _not_used_,
+
+        /* single write. (offset 18 in upm RAM) */
+        0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+        _not_used_, _not_used_, _not_used_, _not_used_,
 
+        /* burst write. (offset 20 in upm RAM) */
+        0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+        0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+        _not_used_, _not_used_, _not_used_, _not_used_,
+        _not_used_, _not_used_, _not_used_, _not_used_,
+
+        /* refresh. (offset 30 in upm RAM) */
+        0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+        0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+        _not_used_, _not_used_, _not_used_, _not_used_,
+
+        /* exception. (offset 3c in upm RAM) */
+        0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
 
 /*
  * Check Board Identity:
@@ -126,10 +128,10 @@ long int initdram (int board_type)
 
     /* perform SDRAM initializsation sequence */
 
-    memctl->memc_mcr  = 0x80002111;	/* SDRAM bank 0 */
-    udelay(1);
+    memctl->memc_mcr  = 0x80002105;	/* SDRAM bank 0 */
+    udelay(200);
     memctl->memc_mcr  = 0x80002230;	/* SDRAM bank 0 - execute twice */
-    udelay(1);
+    udelay(200);
 
     memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
 
diff --git a/include/config_ICU862.h b/include/config_ICU862.h
index 6b40654..21f23e7 100644
--- a/include/config_ICU862.h
+++ b/include/config_ICU862.h
@@ -277,7 +277,7 @@
 #define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
 #define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
 
-#define CFG_OR_TIMING_SDRAM	0x00000900	/* BIH is set		*/
+#define CFG_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
 
 #define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
 #define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)