From: Yang Yingliang <yangyingliang@huawei.com>
Date: Tue, 18 Oct 2022 02:31:48 +0000 (+0800)
Subject: soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=0883dc428c95c123228a4acf340ff21ce5bdd8a3;p=users%2Fjedix%2Flinux-maple.git

soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

[ Upstream commit 756344e7cb1afbb87da8705c20384dddd0dea233 ]

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 25019c16d8ae..98269d056728 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
 				 NULL);
 		if (rc) {
 			pr_err("Could not request IRQ %d\n", g_irq[i]);
-			goto err_unmap;
+			goto err_free_irq;
 		}
 	}
 
@@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
 #endif
 	return 0;
 
+err_free_irq:
+	while (--i >= 0)
+		free_irq(g_irq[i], NULL);
 err_unmap:
 	iounmap(ccache_base);
 	return rc;