From: Bob Picco Date: Tue, 31 Jan 2012 19:02:02 +0000 (-0500) Subject: Revert "bnx2x: fix hw attention handling" X-Git-Tag: v2.6.39-400.9.0~615^2~76 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=05d928ac2e6e658dd37c06c5cc37b37d243ac3fd;p=users%2Fjedix%2Flinux-maple.git Revert "bnx2x: fix hw attention handling" This reverts commit e69f24bc82f6cc28f7df885d401bc79ff3dc6401. --- diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c index 9fdd6c5638ac8..680bcb4f49e57 100644 --- a/drivers/net/bnx2x/bnx2x_main.c +++ b/drivers/net/bnx2x/bnx2x_main.c @@ -4138,7 +4138,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) int igu_seg_id; int port = BP_PORT(bp); int func = BP_FUNC(bp); - int reg_offset, reg_offset_en5; + int reg_offset; u64 section; int index; struct hc_sp_status_block_data sp_sb_data; @@ -4161,8 +4161,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); - reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : - MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { int sindex; /* take care of sig[0]..sig[4] */ @@ -4177,7 +4175,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) * and not 16 between the different groups */ bp->attn_group[index].sig[4] = REG_RD(bp, - reg_offset_en5 + 0x4*index); + reg_offset + 0x10 + 0x4*index); else bp->attn_group[index].sig[4] = 0; } diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 0380b3a8f1c44..86bba25d2d3f4 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -1325,18 +1325,6 @@ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 -/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped - * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC - * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] - * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 - * parity; [31-10] Reserved; */ -#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 -/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped - * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC - * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] - * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 - * parity; [31-10] Reserved; */ -#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector */ #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000