From: Allen Pais Date: Wed, 11 May 2016 13:26:53 +0000 (+0530) Subject: sonoma:correctly recognize sonoma cpu type X-Git-Tag: v4.1.12-92~74^2~17 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=01bd59051e17dc04785211350a05fd337460b86b;p=users%2Fjedix%2Flinux-maple.git sonoma:correctly recognize sonoma cpu type Orabug: 23041920 Signed-off-by: Allen Pais Signed-off-by: Joe Moriarty (cherry picked from commit 72eaed0f66615fe000a63feb7350ba51bf040e06) (cherry picked from commit 70a67f6bfc281c92e9422b1672d0cae30da178df) --- diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h index ad85617b7b263..43c9f0d4208c3 100644 --- a/arch/sparc/include/asm/spitfire.h +++ b/arch/sparc/include/asm/spitfire.h @@ -48,7 +48,7 @@ #define SUN4V_CHIP_SPARC_M6 0x06 #define SUN4V_CHIP_SPARC_M7 0x07 #define SUN4V_CHIP_SPARC_M8 0X08 -#define SUN4V_CHIP_SPARC_SN 0x7a +#define SUN4V_CHIP_SPARC_S7 0x7a #define SUN4V_CHIP_SPARC64X 0x8a #define SUN4V_CHIP_UNKNOWN 0xff diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index 57fff6df94859..848cad738e55d 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c @@ -510,11 +510,12 @@ static void __init sun4v_cpu_probe(void) sparc_cpu_type = "SPARC-M8"; sparc_fpu_type = "SPARC-M8 integrated FPU"; sparc_pmu_type = "sparc-m8"; + break; - case SUN4V_CHIP_SPARC_SN: - sparc_cpu_type = "SPARC-SN (Sonoma)"; - sparc_fpu_type = "SPARC-SN integrated FPU"; - sparc_pmu_type = "sparc-sn"; + case SUN4V_CHIP_SPARC_S7: + sparc_cpu_type = "SPARC-S7 (Sonoma)"; + sparc_fpu_type = "SPARC-S7 integrated FPU"; + sparc_pmu_type = "sparc-s7"; break; case SUN4V_CHIP_SPARC64X: diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index a986884eec89b..9903aa17bb4ee 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -431,6 +431,7 @@ sun4v_chip_type: cmp %g2, 'M' be,pt %xcc, 70f cmp %g2, 'S' + be,pt %xcc, 71f bne,pn %xcc, 49f nop @@ -453,12 +454,15 @@ sun4v_chip_type: cmp %g2, '8' be,pt %xcc, 5f mov SUN4V_CHIP_SPARC_M8, %g4 - cmp %g2, 'N' + ba,pt %xcc, 49f + nop +71: + ldub [%g1 + 7], %g2 + cmp %g2, '7' be,pt %xcc, 5f - mov SUN4V_CHIP_SPARC_SN, %g4 + mov SUN4V_CHIP_SPARC_S7, %g4 ba,pt %xcc, 49f nop - 91: sethi %hi(prom_cpu_compatible), %g1 or %g1, %lo(prom_cpu_compatible), %g1 ldub [%g1 + 17], %g2 @@ -618,6 +622,9 @@ niagara_tlb_fixup: be,pt %xcc, niagara4_patch nop cmp %g1, SUN4V_CHIP_SPARC_M7 + be,pt %xcc, niagara4_patch + nop + cmp %g1, SUN4V_CHIP_SPARC_S7 be,pt %xcc, niagara4_patch nop diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index ba1b5143854da..1b4ea9124b9e7 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c @@ -285,7 +285,8 @@ static void __init sun4v_patch(void) sun4v_patch_2insn_range(&__sun4v_2insn_patch, &__sun4v_2insn_patch_end); - if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7) + if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7) sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, &__sun_m7_2insn_patch_end); @@ -524,6 +525,7 @@ static void __init init_sparc64_elf_hwcap(void) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7 || sun4v_chip_type == SUN4V_CHIP_SPARC64X) cap |= HWCAP_SPARC_BLKINIT; if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || @@ -532,6 +534,7 @@ static void __init init_sparc64_elf_hwcap(void) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7 || sun4v_chip_type == SUN4V_CHIP_SPARC64X) cap |= HWCAP_SPARC_N2; } @@ -561,6 +564,7 @@ static void __init init_sparc64_elf_hwcap(void) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7 || sun4v_chip_type == SUN4V_CHIP_SPARC64X) cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT | @@ -570,11 +574,13 @@ static void __init init_sparc64_elf_hwcap(void) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7 || sun4v_chip_type == SUN4V_CHIP_SPARC64X) cap |= (AV_SPARC_FMAF | AV_SPARC_HPC); if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || - sun4v_chip_type == SUN4V_CHIP_NIAGARA5) + sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || + sun4v_chip_type == SUN4V_CHIP_SPARC_S7) cap |= AV_SPARC_VIS3; } } diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 12b3cafd0f4f9..012132d71e1c9 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -2164,6 +2164,7 @@ static void __init setup_page_offset(void) max_phys_bits = 47; break; case SUN4V_CHIP_SPARC_M7: + case SUN4V_CHIP_SPARC_S7: default: /* M7 and later support 52-bit virtual addresses. */ sparc64_va_hole_top = 0xfff8000000000000UL; @@ -2381,6 +2382,7 @@ static void __init sun4v_linear_pte_xor_finalize(void) */ switch (sun4v_chip_type) { case SUN4V_CHIP_SPARC_M7: + case SUN4V_CHIP_SPARC_S7: pagecv_flag = 0x00; break; default: @@ -2532,6 +2534,7 @@ void __init paging_init(void) */ switch (sun4v_chip_type) { case SUN4V_CHIP_SPARC_M7: + case SUN4V_CHIP_SPARC_S7: page_cache4v_flag = _PAGE_CP_4V; break; default: