Those names don't represent well the meaning for those fields.
So, rename them to be meaningful.
As "is_csrows" is used to indicate that a layer is part of the
virtual csrow, let's name it as is_virt_csrows.
As "GET_POS" is used to get the EDAC mci dimm_info pointer for
a given layer address, let's call it as "EDAC_DIMM_PTR".
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
ret = -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = pvt->csels[0].b_cnt;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = pvt->channel_count;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, false, 0);
if (!mci)
goto err_siblings;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = AMD76X_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = 1;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (mci == NULL)
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = 1;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = num_chans;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, false,
sizeof(struct cell_edac_priv));
if (mci == NULL)
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = CPC925_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = nr_channels;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, false,
sizeof(struct cpc925_mc_pdata));
if (!mci) {
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = E752X_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = drc_chan + 1;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
false, sizeof(*pvt));
if (mci == NULL)
*/
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = E7XXX_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = drc_chan + 1;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (mci == NULL)
return -ENOMEM;
tot_csrows = 1;
for (i = 0; i < n_layers; i++) {
tot_dimms *= layers[i].size;
- if (layers[i].is_csrow)
+ if (layers[i].is_virt_csrow)
tot_csrows *= layers[i].size;
else
tot_cschannels *= layers[i].size;
/* Increment csrow location */
if (!rev_order) {
for (j = n_layers - 1; j >= 0; j--)
- if (!layers[j].is_csrow)
+ if (!layers[j].is_virt_csrow)
break;
chn++;
if (chn == tot_cschannels) {
}
} else {
for (j = n_layers - 1; j >= 0; j--)
- if (layers[j].is_csrow)
+ if (layers[j].is_virt_csrow)
break;
row++;
if (row == tot_csrows) {
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = I3000_RANKS / nr_channels;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = nr_channels;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (!mci)
return -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = I3200_DIMMS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = nr_channels;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
false, sizeof(struct i3200_priv));
if (!mci)
if (!MTR_DIMMS_PRESENT(mtr))
continue;
- dimm = GET_POS(mci->layers, mci->dimms, mci->n_layers,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
channel / MAX_BRANCHES,
channel % MAX_BRANCHES, slot);
layers[0].type = EDAC_MC_LAYER_BRANCH;
layers[0].size = MAX_BRANCHES;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = num_channels / MAX_BRANCHES;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
layers[2].type = EDAC_MC_LAYER_SLOT;
layers[2].size = num_dimms_per_channel;
- layers[2].is_csrow = true;
+ layers[2].is_virt_csrow = true;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (mci == NULL)
if (!npages)
continue;
- dimm = GET_POS(mci->layers, mci->dimms, mci->n_layers,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
chan, rank, 0);
dimm->nr_pages = npages;
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = 2;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_SLOT;
layers[1].size = ranksperch;
- layers[1].is_csrow = true;
+ layers[1].is_virt_csrow = true;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
false, sizeof(*priv));
if (!mci) {
if (!MTR_DIMMS_PRESENT(mtr))
continue;
- dimm = GET_POS(mci->layers, mci->dimms, mci->n_layers,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
channel / 2, channel % 2, slot);
size_mb = pvt->dimm_info[slot][channel].megabytes;
*/
layers[0].type = EDAC_MC_LAYER_BRANCH;
layers[0].size = MAX_BRANCHES;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = CHANNELS_PER_BRANCH;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
layers[2].type = EDAC_MC_LAYER_SLOT;
layers[2].size = DIMMS_PER_CHANNEL;
- layers[2].is_csrow = true;
+ layers[2].is_virt_csrow = true;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (mci == NULL)
for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
int channel = to_channel(ch, branch);
- dimm = GET_POS(mci->layers, mci->dimms,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
mci->n_layers, branch, ch, slot);
dinfo = &pvt->dimm_info[slot][channel];
/* allocate a new MC control structure */
layers[0].type = EDAC_MC_LAYER_BRANCH;
layers[0].size = MAX_BRANCHES;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = MAX_CH_PER_BRANCH;
- layers[1].is_csrow = true;
+ layers[1].is_virt_csrow = true;
layers[2].type = EDAC_MC_LAYER_SLOT;
layers[2].size = MAX_SLOTS;
- layers[2].is_csrow = true;
+ layers[2].is_virt_csrow = true;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (mci == NULL)
if (!DIMM_PRESENT(dimm_dod[j]))
continue;
- dimm = GET_POS(mci->layers, mci->dimms, mci->n_layers,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
i, j, 0);
banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = NUM_CHANS;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_SLOT;
layers[1].size = MAX_DIMMS;
- layers[1].is_csrow = true;
+ layers[1].is_virt_csrow = true;
mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
false, sizeof(*pvt));
if (unlikely(!mci))
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = I82443BXGX_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = I82443BXGX_NR_CHANS;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (mci == NULL)
return -ENOMEM;
*/
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = 2;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_SLOT;
layers[1].size = 8;
- layers[1].is_csrow = true;
+ layers[1].is_virt_csrow = true;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (!mci)
return -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = I82875P_NR_CSROWS(nr_chans);
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = nr_chans;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (!mci) {
rc = -ENOMEM;
/* assuming only one controller, index thus is 0 */
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = I82975X_NR_DIMMS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = I82975X_NR_CSROWS(chans);
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, sizeof(*pvt));
if (!mci) {
rc = -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = 4;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = 1;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, false,
sizeof(*pdata));
if (!mci) {
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = 1;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = 1;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, false,
sizeof(struct mv64x60_mc_pdata));
if (!mci) {
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = PASEMI_EDAC_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = PASEMI_EDAC_NR_CHANS;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, false,
0);
if (mci == NULL)
*/
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = ppc4xx_edac_nr_csrows;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = ppc4xx_edac_nr_chans;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
false, sizeof(struct ppc4xx_edac_pdata));
if (mci == NULL) {
debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = R82600_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = R82600_NR_CHANS;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (mci == NULL)
return -ENOMEM;
u32 mtr;
for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
- dimm = GET_POS(mci->layers, mci->dimms, mci->n_layers,
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
i, j, 0);
pci_read_config_dword(pvt->pci_tad[i],
mtr_regs[j], &mtr);
/* allocate a new MC control structure */
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = NUM_CHANNELS;
- layers[0].is_csrow = false;
+ layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_SLOT;
layers[1].size = MAX_DIMMS;
- layers[1].is_csrow = true;
+ layers[1].is_virt_csrow = true;
mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
false, sizeof(*pvt));
/* A TILE MC has a single channel and one chip-select row. */
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = TILE_EDAC_NR_CSROWS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = TILE_EDAC_NR_CHANS;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, false,
sizeof(struct tile_edac_priv));
if (mci == NULL)
/* FIXME: unconventional pvt_info usage */
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = X38_RANKS;
- layers[0].is_csrow = true;
+ layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = x38_channel_num;
- layers[1].is_csrow = false;
+ layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, false, 0);
if (!mci)
return -ENOMEM;
* struct edac_mc_layer - describes the memory controller hierarchy
* @layer: layer type
* @size:maximum size of the layer
- * @is_csrow: This layer is part of the "csrow" when old API
+ * @is_virt_csrow: This layer is part of the "csrow" when old API
* compatibility mode is enabled. Otherwise, it is
* a channel
*/
struct edac_mc_layer {
enum edac_mc_layer_type type;
unsigned size;
- bool is_csrow;
+ bool is_virt_csrow;
};
/*
__i; \
})
-#define GET_POS(layers, var, nlayers, lay0, lay1, lay2) ({ \
+#define EDAC_DIMM_PTR(layers, var, nlayers, lay0, lay1, lay2) ({ \
typeof(*var) __p; \
int ___i = GET_OFFSET(layers, nlayers, lay0, lay1, lay2); \
if (___i < 0) \