arm64: dts: qcom: x1e80100: Describe the SDHC controllers

The X Elite platform features two SDHC v5 controllers.

Describe the controllers along with the pin configuration in TLMM
for the SDC2, since they are hardwired and cannot be muxed to any
other function. The SDC4 pin configuration can be muxed to different
functions, so leave those to board specific dts.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org
[bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..18fb182c185c0932feb15b8a4a5c450814e68991 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4094,6 +4094,108 @@
                        #interconnect-cells = <2>;
                };
 
+               sdhc_2: mmc@8804000 {
+                       compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0 0x08804000 0 0x1000>;
+
+                       interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+
+                       clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                                <&gcc GCC_SDCC2_APPS_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "iface", "core", "xo";
+                       iommus = <&apps_smmu 0x520 0>;
+                       qcom,dll-config = <0x0007642c>;
+                       qcom,ddr-config = <0x80040868>;
+                       power-domains = <&rpmhpd RPMHPD_CX>;
+                       operating-points-v2 = <&sdhc2_opp_table>;
+
+                       interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "sdhc-ddr", "cpu-sdhc";
+                       bus-width = <4>;
+                       dma-coherent;
+
+                       status = "disabled";
+
+                       sdhc2_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-19200000 {
+                                       opp-hz = /bits/ 64 <19200000>;
+                                       required-opps = <&rpmhpd_opp_min_svs>;
+                               };
+
+                               opp-50000000 {
+                                       opp-hz = /bits/ 64 <50000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-202000000 {
+                                       opp-hz = /bits/ 64 <202000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+                       };
+               };
+
+               sdhc_4: mmc@8844000 {
+                       compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0 0x08844000 0 0x1000>;
+
+                       interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq", "pwr_irq";
+
+                       clocks = <&gcc GCC_SDCC4_AHB_CLK>,
+                                <&gcc GCC_SDCC4_APPS_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "iface", "core", "xo";
+                       iommus = <&apps_smmu 0x160 0>;
+                       qcom,dll-config = <0x0007642c>;
+                       qcom,ddr-config = <0x80040868>;
+                       power-domains = <&rpmhpd RPMHPD_CX>;
+                       operating-points-v2 = <&sdhc4_opp_table>;
+
+                       interconnects = <&aggre2_noc MASTER_SDCC_4 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_4 0>;
+                       interconnect-names = "sdhc-ddr", "cpu-sdhc";
+                       bus-width = <4>;
+                       dma-coherent;
+
+                       status = "disabled";
+
+                       sdhc4_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-19200000 {
+                                       opp-hz = /bits/ 64 <19200000>;
+                                       required-opps = <&rpmhpd_opp_min_svs>;
+                               };
+
+                               opp-50000000 {
+                                       opp-hz = /bits/ 64 <50000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-202000000 {
+                                       opp-hz = /bits/ 64 <202000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+                       };
+               };
+
                usb_2_hsphy: phy@88e0000 {
                        compatible = "qcom,x1e80100-snps-eusb2-phy",
                                     "qcom,sm8550-snps-eusb2-phy";
@@ -5852,6 +5954,46 @@
                                        bias-disable;
                                };
                        };
+
+                       sdc2_default: sdc2-default-state {
+                               clk-pins {
+                                       pins = "sdc2_clk";
+                                       drive-strength = <16>;
+                                       bias-disable;
+                               };
+
+                               cmd-pins {
+                                       pins = "sdc2_cmd";
+                                       drive-strength = <10>;
+                                       bias-pull-up;
+                               };
+
+                               data-pins {
+                                       pins = "sdc2_data";
+                                       drive-strength = <10>;
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdc2_sleep: sdc2-sleep-state {
+                               clk-pins {
+                                       pins = "sdc2_clk";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                               };
+
+                               cmd-pins {
+                                       pins = "sdc2_cmd";
+                                       drive-strength = <2>;
+                                       bias-pull-up;
+                               };
+
+                               data-pins {
+                                       pins = "sdc2_data";
+                                       drive-strength = <2>;
+                                       bias-pull-up;
+                               };
+                       };
                };
 
                apps_smmu: iommu@15000000 {