drm/i915/guc: Enable DUAL_QUEUE_WA for newer platforms

For newer platforms (post DG2) hardware intentionally stalls on
submisstion of concurrent submissions on RCS and CCS of different
address spaces.  With this workaround GuC will never schedule such
conlicting contexts; preventing detection of a stall as a hang.

GuC specs recommend to enable this for all platforms starting from MTL
supporting CCS.

v2: Use existing macros for version check. (Jani)
v3: Reword explanation for clarity. Remove unneeded parens. Remove
    accidental comment change. (Daniele)

Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://lore.kernel.org/r/20250502223924.94628-1-julia.filipchuk@intel.com

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 5949ff0b0161ffda08058daddaf202c1c0941103..553daf32c0b540bf624a9603f2d13cf5c1364a2e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -313,8 +313,13 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
         *
         * The same WA bit is used for both and 22011391025 is applicable to
         * all DG2.
+        *
+        * Platforms post DG2 prevent this issue in hardware by stalling
+        * submissions. With this flag GuC will schedule as to avoid such
+        * stalls.
         */
-       if (IS_DG2(gt->i915))
+       if (IS_DG2(gt->i915) ||
+           (CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)))
                flags |= GUC_WA_DUAL_QUEUE;
 
        /* Wa_22011802037: graphics version 11/12 */