net: stmmac: dwxgmac: Finish the Flow Control implementation

Finish the implementation of Flow Control feature. In order for it to
work correctly we need to set EHFC bit and the correct threshold values
for activating and deactivating it.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 37d5e6fe74737f6c82acc223e2c93b043b7bb9f4..085b700a4994e599ec5ff2044c690a614f5ac4e6 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -143,6 +143,11 @@
 #define XGMAC_RSF                      BIT(5)
 #define XGMAC_RTC                      GENMASK(1, 0)
 #define XGMAC_RTC_SHIFT                        0
+#define XGMAC_MTL_RXQ_FLOW_CONTROL(x)  (0x00001150 + (0x80 * (x)))
+#define XGMAC_RFD                      GENMASK(31, 17)
+#define XGMAC_RFD_SHIFT                        17
+#define XGMAC_RFA                      GENMASK(15, 1)
+#define XGMAC_RFA_SHIFT                        1
 #define XGMAC_MTL_QINTEN(x)            (0x00001170 + (0x80 * (x)))
 #define XGMAC_RXOIE                    BIT(16)
 #define XGMAC_MTL_QINT_STATUS(x)       (0x00001174 + (0x80 * (x)))

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 2ba712b48a89ab3f71997666845b1804ef450e88..e79037f511e16c6d8bc7085c1612e3f5b0d81912 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -147,6 +147,52 @@ static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
        value &= ~XGMAC_RQS;
        value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
 
+       if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
+               u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
+               unsigned int rfd, rfa;
+
+               value |= XGMAC_EHFC;
+
+               /* Set Threshold for Activating Flow Control to min 2 frames,
+                * i.e. 1500 * 2 = 3000 bytes.
+                *
+                * Set Threshold for Deactivating Flow Control to min 1 frame,
+                * i.e. 1500 bytes.
+                */
+               switch (fifosz) {
+               case 4096:
+                       /* This violates the above formula because of FIFO size
+                        * limit therefore overflow may occur in spite of this.
+                        */
+                       rfd = 0x03; /* Full-2.5K */
+                       rfa = 0x01; /* Full-1.5K */
+                       break;
+
+               case 8192:
+                       rfd = 0x06; /* Full-4K */
+                       rfa = 0x0a; /* Full-6K */
+                       break;
+
+               case 16384:
+                       rfd = 0x06; /* Full-4K */
+                       rfa = 0x12; /* Full-10K */
+                       break;
+
+               default:
+                       rfd = 0x06; /* Full-4K */
+                       rfa = 0x1e; /* Full-16K */
+                       break;
+               }
+
+               flow &= ~XGMAC_RFD;
+               flow |= rfd << XGMAC_RFD_SHIFT;
+
+               flow &= ~XGMAC_RFA;
+               flow |= rfa << XGMAC_RFA_SHIFT;
+
+               writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
+       }
+
        writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
 
        /* Enable MTL RX overflow */