drm/amdgpu:kiq reg access need timeout(v2)

this is to prevent fence forever waiting if FLR occured
during register accessing.

v2:
use define instead of hardcode for the timeout msec

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 61fcf264c24713301d2da9f5bef7c0a1dd82aa53..8a081e162d13cb6f6cc6b674fd82cd52180cb40c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,6 +22,7 @@
  */
 
 #include "amdgpu.h"
+#define MAX_KIQ_REG_WAIT       100000
 
 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
 {
@@ -128,10 +129,12 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
        amdgpu_ring_commit(ring);
        mutex_unlock(&kiq->ring_mutex);
 
-       r = dma_fence_wait(f, false);
-       if (r)
-               DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+       r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
        dma_fence_put(f);
+       if (r < 1) {
+               DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+               return ~0;
+       }
 
        val = adev->wb.wb[adev->virt.reg_val_offs];
 
@@ -154,8 +157,8 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
        amdgpu_ring_commit(ring);
        mutex_unlock(&kiq->ring_mutex);
 
-       r = dma_fence_wait(f, false);
-       if (r)
+       r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
+       if (r < 1)
                DRM_ERROR("wait for kiq fence error: %ld.\n", r);
        dma_fence_put(f);
 }