}
 
        /* kmap the object */
-       base = drm_gem_vram_kmap_at(gbo, true, NULL, &ast->cache_kmap);
+       base = drm_gem_vram_kmap(gbo, true, NULL);
        if (IS_ERR(base)) {
                ret = PTR_ERR(base);
                goto fail;
        }
 
        ast->cursor_cache = obj;
-       ast->cursor_cache_gpu_addr = gpu_addr;
-       DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
        return 0;
 fail:
        return ret;
        struct ast_private *ast = dev->dev_private;
        struct drm_gem_vram_object *gbo =
                drm_gem_vram_of_gem(ast->cursor_cache);
-       drm_gem_vram_kunmap_at(gbo, &ast->cache_kmap);
+       drm_gem_vram_kunmap(gbo);
        drm_gem_vram_unpin(gbo);
        drm_gem_object_put_unlocked(ast->cursor_cache);
 }
        struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
        struct drm_gem_object *obj;
        struct drm_gem_vram_object *gbo;
-       s64 gpu_addr;
+       s64 dst_gpu;
+       u64 gpu_addr;
        u32 csum;
        int ret;
        struct ttm_bo_kmap_obj uobj_map;
        if (src_isiomem == true)
                DRM_ERROR("src cursor bo should be in main memory\n");
 
-       dst = drm_gem_vram_kmap_at(drm_gem_vram_of_gem(ast->cursor_cache),
-                                  false, &dst_isiomem, &ast->cache_kmap);
+       dst = drm_gem_vram_kmap(drm_gem_vram_of_gem(ast->cursor_cache),
+                               false, &dst_isiomem);
        if (IS_ERR(dst)) {
                ret = PTR_ERR(dst);
                goto fail_unlock;
        }
        if (dst_isiomem == false)
                DRM_ERROR("dst bo should be in VRAM\n");
+       dst_gpu = drm_gem_vram_offset(drm_gem_vram_of_gem(ast->cursor_cache));
+       if (dst_gpu < 0) {
+               ret = (int)dst_gpu;
+               goto fail_unlock;
+       }
 
        dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
 
 
        /* write checksum + signature */
        {
-               u8 *dst = drm_gem_vram_kmap_at(drm_gem_vram_of_gem(ast->cursor_cache),
-                                              false, NULL, &ast->cache_kmap);
+               struct drm_gem_vram_object *dst_gbo =
+                       drm_gem_vram_of_gem(ast->cursor_cache);
+               u8 *dst = drm_gem_vram_kmap(dst_gbo, false, NULL);
                dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
                writel(csum, dst);
                writel(width, dst + AST_HWC_SIGNATURE_SizeX);
                writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
 
                /* set pattern offset */
-               gpu_addr = ast->cursor_cache_gpu_addr;
+               gpu_addr = (u64)dst_gpu;
                gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
                gpu_addr >>= 3;
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
        }
-       ast_crtc->cursor_width = width;
-       ast_crtc->cursor_height = height;
        ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
        ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
 
        int x_offset, y_offset;
        u8 *sig;
 
-       sig = drm_gem_vram_kmap_at(drm_gem_vram_of_gem(ast->cursor_cache),
-                                  false, NULL, &ast->cache_kmap);
+       sig = drm_gem_vram_kmap(drm_gem_vram_of_gem(ast->cursor_cache),
+                               false, NULL);
        sig += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
        writel(x, sig + AST_HWC_SIGNATURE_X);
        writel(y, sig + AST_HWC_SIGNATURE_Y);