#define        CSIO_HWF_HOST_INTR_ENABLED      0x00000200      /* Are host interrupts
                                                         * enabled?
                                                         */
+#define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400   /* Is PCIe relaxed
+                                                        * ordering enabled
+                                                        */
 
 #define csio_is_hw_intr_enabled(__hw)  \
                                ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
 
        uint32_t iq_start_stop = (iq_params->iq_start)  ?
                                        FW_IQ_CMD_IQSTART_F :
                                        FW_IQ_CMD_IQSTOP_F;
+       int relaxed = !(hw->flags & CSIO_HWF_ROOT_NO_RELAXED_ORDERING);
 
        /*
         * If this IQ write is cascaded with IQ alloc request, do not
                cmdp->iqns_to_fl0congen |= htonl(
                        FW_IQ_CMD_FL0HOSTFCMODE_V(iq_params->fl0hostfcmode)|
                        FW_IQ_CMD_FL0CPRIO_V(iq_params->fl0cprio)       |
+                       FW_IQ_CMD_FL0FETCHRO_V(relaxed)                 |
+                       FW_IQ_CMD_FL0DATARO_V(relaxed)                  |
                        FW_IQ_CMD_FL0PADEN_V(iq_params->fl0paden)       |
                        FW_IQ_CMD_FL0PACKEN_V(iq_params->fl0packen));
                cmdp->fl0dcaen_to_fl0cidxfthresh |= htons(