* 2. power off the acp tiles
         * 3. check and enter ulv state
         */
-       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
        return 0;
 }
 
         * 2. turn on acp clock
         * 3. power on acp tiles
         */
-       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
        return 0;
 }
 
                            ip_block->version->major, ip_block->version->minor);
        /* -ENODEV means board uses AZ rather than ACP */
        if (r == -ENODEV) {
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
                return 0;
        } else if (r) {
                return r;
 
        /* return early if no ACP */
        if (!adev->acp.acp_genpd) {
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
                return 0;
        }
 
 
        /* power up on suspend */
        if (!adev->acp.acp_cell)
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
        return 0;
 }
 
 
        /* power down again on resume */
        if (!adev->acp.acp_cell)
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
        return 0;
 }
 
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        bool enable = (state == AMD_PG_STATE_GATE);
 
-       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
+       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
 
        return 0;
 }
 
        WARN_ON_ONCE(adev->gfx.gfx_off_state);
        WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
 
-       if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
+       if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))
                adev->gfx.gfx_off_state = true;
 }
 
 
                        /* If going to s2idle, no need to wait */
                        if (adev->in_s0ix) {
                                if (!amdgpu_dpm_set_powergating_by_smu(adev,
-                                               AMD_IP_BLOCK_TYPE_GFX, true))
+                                               AMD_IP_BLOCK_TYPE_GFX, true, 0))
                                        adev->gfx.gfx_off_state = true;
                        } else {
                                schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
                        cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 
                        if (adev->gfx.gfx_off_state &&
-                           !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
+                           !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {
                                adev->gfx.gfx_off_state = false;
 
                                if (adev->gfx.funcs->init_spm_golden) {
 
            (adev->asic_type == CHIP_POLARIS12) ||
            (adev->asic_type == CHIP_VEGAM))
                /* Send msg to SMU via Powerplay */
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);
 
        WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
 }
 
        if (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
                amdgpu_dpm_set_powergating_by_smu(adev,
                                                  AMD_IP_BLOCK_TYPE_GMC,
-                                                 enable);
+                                                 enable, 0);
 }
 
 static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
        struct amdgpu_device *adev = ip_block->adev;
 
        if (adev->flags & AMD_IS_APU)
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
 
        if (!amdgpu_sriov_vf(adev))
                sdma_v4_0_init_golden_registers(adev);
        sdma_v4_0_enable(adev, false);
 
        if (adev->flags & AMD_IS_APU)
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0);
 
        return 0;
 }
 
        idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
        if (idle_work_unexecuted) {
                if (adev->pm.dpm_enabled)
-                       amdgpu_dpm_enable_uvd(adev, false);
+                       amdgpu_dpm_enable_vcn(adev, false);
        }
 
        r = vcn_v1_0_hw_fini(ip_block);
        if (fences == 0) {
                amdgpu_gfx_off_ctrl(adev, true);
                if (adev->pm.dpm_enabled)
-                       amdgpu_dpm_enable_uvd(adev, false);
+                       amdgpu_dpm_enable_vcn(adev, false);
                else
                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
                               AMD_PG_STATE_GATE);
        if (set_clocks) {
                amdgpu_gfx_off_ctrl(adev, false);
                if (adev->pm.dpm_enabled)
-                       amdgpu_dpm_enable_uvd(adev, true);
+                       amdgpu_dpm_enable_vcn(adev, true);
                else
                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
                               AMD_PG_STATE_UNGATE);
 
        int i, j, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
                return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
 
 power_off:
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        int i, j, k, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->vcn.harvest_config & (1 << i))
        }
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        int i, j, k, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->vcn.harvest_config & (1 << i))
        }
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        int i, j, k, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->vcn.harvest_config & (1 << i))
        }
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        uint32_t tmp;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
        }
 Done:
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        int i, j, k, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->vcn.harvest_config & (1 << i))
        }
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        int i, j, k, r;
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, true);
+               amdgpu_dpm_enable_vcn(adev, true);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                if (adev->vcn.harvest_config & (1 << i))
        }
 
        if (adev->pm.dpm_enabled)
-               amdgpu_dpm_enable_uvd(adev, false);
+               amdgpu_dpm_enable_vcn(adev, false);
 
        return 0;
 }
 
        return ret;
 }
 
-int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate)
+int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
+                                      uint32_t block_type,
+                                      bool gate,
+                                      int inst)
 {
        int ret = 0;
        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
        enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
+       bool is_vcn = (block_type == AMD_IP_BLOCK_TYPE_UVD || block_type == AMD_IP_BLOCK_TYPE_VCN);
 
-       if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
+       if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
+                       (!is_vcn || adev->vcn.num_vcn_inst == 1)) {
                dev_dbg(adev->dev, "IP block%d already in the target %s state!",
                                block_type, gate ? "gate" : "ungate");
                return 0;
                                (adev)->powerplay.pp_handle, block_type, gate, 0));
                break;
        case AMD_IP_BLOCK_TYPE_VCN:
-               if (pp_funcs && pp_funcs->set_powergating_by_smu) {
-                       for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
-                               ret = (pp_funcs->set_powergating_by_smu(
-                                       (adev)->powerplay.pp_handle, block_type, gate, i));
-               }
+               if (pp_funcs && pp_funcs->set_powergating_by_smu)
+                       ret = (pp_funcs->set_powergating_by_smu(
+                               (adev)->powerplay.pp_handle, block_type, gate, inst));
                break;
        default:
                break;
                return;
        }
 
-       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
+       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);
        if (ret)
                DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
                          enable ? "enable" : "disable", ret);
 }
 
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable)
+{
+       int i, ret = 0;
+
+       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+               ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, i);
+               if (ret)
+                       DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
+                                 enable ? "enable" : "disable", ret);
+       }
+}
+
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
        int ret = 0;
                return;
        }
 
-       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
+       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);
        if (ret)
                DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
                          enable ? "enable" : "disable", ret);
 {
        int ret = 0;
 
-       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
+       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);
        if (ret)
                DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
                          enable ? "enable" : "disable", ret);
 {
        int ret = 0;
 
-       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable);
+       ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);
        if (ret)
                DRM_ERROR("Dpm %s vpe failed, ret = %d.\n",
                          enable ? "enable" : "disable", ret);
 
 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
 
 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
-                                     uint32_t block_type, bool gate);
+                                     uint32_t block_type, bool gate, int inst);
 
 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
 
 
 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable);
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
 void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);