crypto: hisilicon/qm - fix the type value of aeq

The type of aeq has only 4bits in dw0 17 to 20bits, but 15bits(17 to
31bits) are read in function qm_aeq_thread(). The remaining 11bits(21
to 31bits) are reserved for aeq, but may not be 0. To avoid getting
incorrect value of type, other bits are cleared.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 1638c0a7df310418c9ecb84f4e564caa542b89f1..458d1fe42a246cf9f0a050cd8ad0ce0d427bbccc 100644 (file)
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -69,6 +69,7 @@
 
 #define QM_AEQE_PHASE(aeqe)            ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
 #define QM_AEQE_TYPE_SHIFT             17
+#define QM_AEQE_TYPE_MASK              0xf
 #define QM_AEQE_CQN_MASK               GENMASK(15, 0)
 #define QM_CQ_OVERFLOW                 0
 #define QM_EQ_OVERFLOW                 1
@@ -1024,7 +1025,8 @@ static irqreturn_t qm_aeq_thread(int irq, void *data)
        u32 type, qp_id;
 
        while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
-               type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;
+               type = (le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT) &
+                       QM_AEQE_TYPE_MASK;
                qp_id = le32_to_cpu(aeqe->dw0) & QM_AEQE_CQN_MASK;
 
                switch (type) {