drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY

The PSR code has no business mucking around with the
vblank delay. Currently nothing that depends on knowing
the exact vblank start scanline (eg. vblank evasion)
is aware of this and so will not work correctly.

The w/a seems to be for pre-production hw only, so let's
just nuke it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 928664b5faffe70717a1033c09a342f519b582bc..4c93af6244b4e033e11692ee8ebbd5e049118ffd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1163,13 +1163,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                        intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
                                     ADLP_1_BASED_X_GRANULARITY);
 
-               /* Wa_16011168373:adl-p */
-               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
-                       intel_de_rmw(dev_priv,
-                                    TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
-                                    TRANS_SET_CONTEXT_LATENCY_MASK,
-                                    TRANS_SET_CONTEXT_LATENCY_VALUE(1));
-
                /* Wa_16012604467:adlp,mtl[a0,b0] */
                if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
@@ -1334,12 +1327,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
                             wa_16013835468_bit_get(intel_dp), 0);
 
        if (intel_dp->psr.psr2_enabled) {
-               /* Wa_16011168373:adl-p */
-               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
-                       intel_de_rmw(dev_priv,
-                                    TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
-                                    TRANS_SET_CONTEXT_LATENCY_MASK, 0);
-
                /* Wa_16012604467:adlp,mtl[a0,b0] */
                if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,