struct intel_psr *psr = &intel_dp->psr;
intel_wakeref_t wakeref;
bool enabled;
- u32 val;
+ u32 val, psr2_ctl;
intel_psr_sink_capability(intel_dp, m);
if (psr->panel_replay_enabled) {
val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
+
+ if (intel_dp_is_edp(intel_dp))
+ psr2_ctl = intel_de_read(dev_priv,
+ EDP_PSR2_CTL(dev_priv,
+ cpu_transcoder));
+
enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
} else if (psr->sel_update_enabled) {
val = intel_de_read(dev_priv,
}
seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
str_enabled_disabled(enabled), val);
+ if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
+ seq_printf(m, "PSR2_CTL: 0x%08x\n",
+ psr2_ctl);
psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
psr->busy_frontbuffer_bits);