Edited report from pahole on amd64 host:
struct PCNetState_st {
...
uint16_t bcr[32]; /* 340 64 */
/* XXX 4 bytes hole, try to pack */
...
int tx_busy; /* 4520 4 */
/* XXX 4 bytes hole, try to pack */
qemu_irq irq; /* 4528 8 */
void (*phys_mem_read)(void *, target_phys_addr_t, uint8_t *, int, int); /* 4536 8 */
/* --- cacheline 71 boundary (4544 bytes) --- */
void (*phys_mem_write)(void *, target_phys_addr_t, uint8_t *, int, int); /* 4544 8 */
void * dma_opaque; /* 4552 8 */
int looptest; /* 4560 4 */
/* size: 4568, cachelines: 72 */
/* sum members: 4556, holes: 2, sum holes: 8 */
/* padding: 4 */
/* last cacheline: 24 bytes */
}; /* definitions: 2 */
Fix by rearranging the structure to avoid padding.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
uint8_t prom[16];
uint16_t csr[128];
uint16_t bcr[32];
+ int xmit_pos;
uint64_t timer;
MemoryRegion mmio;
- int xmit_pos;
uint8_t buffer[4096];
- int tx_busy;
qemu_irq irq;
void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
+ int tx_busy;
int looptest;
};