Offset &= 0x3f;
 
-       if (priv->rf_chip == RF_8256) {
-               rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
-               if (Offset >= 31) {
-                       priv->rf_reg_0value[eRFPath] |= 0x140;
-                       rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
-                                         bMaskDWord,
-                                         (priv->rf_reg_0value[eRFPath] << 16));
-                       NewOffset = Offset - 30;
-               } else if (Offset >= 16) {
-                       priv->rf_reg_0value[eRFPath] |= 0x100;
-                       priv->rf_reg_0value[eRFPath] &= (~0x40);
-                       rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
-                                         bMaskDWord,
-                                         (priv->rf_reg_0value[eRFPath] << 16));
-
-                       NewOffset = Offset - 15;
-               } else
-                       NewOffset = Offset;
+       rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
+       if (Offset >= 31) {
+               priv->rf_reg_0value[eRFPath] |= 0x140;
+               rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
+                                 bMaskDWord,
+                                 (priv->rf_reg_0value[eRFPath] << 16));
+               NewOffset = Offset - 30;
+       } else if (Offset >= 16) {
+               priv->rf_reg_0value[eRFPath] |= 0x100;
+               priv->rf_reg_0value[eRFPath] &= (~0x40);
+               rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
+                                 bMaskDWord,
+                                 (priv->rf_reg_0value[eRFPath] << 16));
+               NewOffset = Offset - 15;
        } else {
                NewOffset = Offset;
        }
        ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
                                bLSSIReadBackData);
 
-       if (priv->rf_chip == RF_8256) {
-               priv->rf_reg_0value[eRFPath] &= 0xebf;
-
-               rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
-                                 (priv->rf_reg_0value[eRFPath] << 16));
+       priv->rf_reg_0value[eRFPath] &= 0xebf;
 
-               rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
-       }
+       rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
+                         (priv->rf_reg_0value[eRFPath] << 16));
 
+       rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
 
        return ret;