NoNewPrivs:     0
   Seccomp:        0
   Speculation_Store_Bypass:       thread vulnerable
+  SpeculationIndirectBranch:      conditional enabled
   voluntary_ctxt_switches:        0
   nonvoluntary_ctxt_switches:     1
 
  NoNewPrivs                  no_new_privs, like prctl(PR_GET_NO_NEW_PRIV, ...)
  Seccomp                     seccomp mode, like prctl(PR_GET_SECCOMP, ...)
  Speculation_Store_Bypass    speculative store bypass mitigation status
+ SpeculationIndirectBranch   indirect branch speculation mode
  Cpus_allowed                mask of CPUs on which this process may run
  Cpus_allowed_list           Same as previous, but in "list format"
  Mems_allowed                mask of memory nodes allowed to this process
 
                seq_puts(m, "vulnerable");
                break;
        }
+
+       seq_puts(m, "\nSpeculationIndirectBranch:\t");
+       switch (arch_prctl_spec_ctrl_get(p, PR_SPEC_INDIRECT_BRANCH)) {
+       case -EINVAL:
+               seq_puts(m, "unsupported");
+               break;
+       case PR_SPEC_NOT_AFFECTED:
+               seq_puts(m, "not affected");
+               break;
+       case PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE:
+               seq_puts(m, "conditional force disabled");
+               break;
+       case PR_SPEC_PRCTL | PR_SPEC_DISABLE:
+               seq_puts(m, "conditional disabled");
+               break;
+       case PR_SPEC_PRCTL | PR_SPEC_ENABLE:
+               seq_puts(m, "conditional enabled");
+               break;
+       case PR_SPEC_ENABLE:
+               seq_puts(m, "always enabled");
+               break;
+       case PR_SPEC_DISABLE:
+               seq_puts(m, "always disabled");
+               break;
+       default:
+               seq_puts(m, "unknown");
+               break;
+       }
        seq_putc(m, '\n');
 }